| /openbmc/u-boot/arch/x86/cpu/queensbay/ |
| H A D | Kconfig | 29 bool "Add a Chipset Micro Code state machine binary"
31 Select this option to add a Chipset Micro Code state machine binary
37 string "Chipset Micro Code state machine filename"
41 The filename of the file to use as Chipset Micro Code state machine
45 hex "Chipset Micro Code state machine binary location"
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| /openbmc/u-boot/arch/x86/include/asm/ |
| H A D | acpi_s3.h | 87 * chipset_prev_sleep_state() - Get chipset previous sleep state
89 * This returns chipset previous sleep state from ACPI registers.
97 * chipset_clear_sleep_state() - Clear chipset sleep state
99 * This clears chipset sleep state in ACPI registers.
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| H A D | mp.h | 72 * up to the chipset or mainboard to either e820 reserve this area or save this
82 * the device tree unless the chipset or mainboard know the APIC ids
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| H A D | report_platform.h | 12 * This reports information about the CPU and chipset.
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| H A D | irq.h | 43 * @actl_8bit: ACTL register width is 8-bit (for ICH series chipset)
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| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Chassis/Control/ |
| H A D | NMISource.interface.yaml | 42 - name: Chipset
44 Via chipset NMI.
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| /openbmc/u-boot/board/emulation/ |
| H A D | Kconfig | 17 chipset platform and '-M q35', a Q35/ICH9 chipset platform.
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| /openbmc/qemu/target/i386/tcg/system/ |
| H A D | fpu_helper.c | 56 * We get here in response to a write to port F0h. The chipset should in cpu_set_ignne()
60 * do directly what the chipset would do, i.e. deassert FP_IRQ. in cpu_set_ignne()
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| /openbmc/u-boot/board/dfi/dfi-bt700/acpi/ |
| H A D | mainboard.asl | 12 /* TODO: Need add Nuvoton SuperIO chipset NCT6102D ASL codes */
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| /openbmc/u-boot/board/congatec/conga-qeval20-qa3-e3845/acpi/ |
| H A D | mainboard.asl | 12 /* TODO: Need add Winbond SuperIO chipset W83627 ASL codes */
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| /openbmc/u-boot/doc/device-tree-bindings/misc/ |
| H A D | intel,irq-router.txt | 18 be specified. The 8-bit ACTL register is seen on ICH series chipset, like
19 ICH9/Panther Point/etc. On Atom chipset it is a 32-bit register.
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| /openbmc/openpower-proc-control/ |
| H A D | README.md | 3 Contains procedures that interact with the OpenPower nest chipset.
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| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Common/ |
| H A D | FaultLogType.interface.yaml | 14 Collection of processor and chipset register values typically
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| /openbmc/u-boot/doc/driver-model/ |
| H A D | pci-info.txt | 97 to a downstream device Topcliff chipset. Inside Topcliff chipset, it has a
98 PCIe-to-PCI bridge and all the chipset integrated devices like the PCI UART
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| /openbmc/openbmc/meta-openembedded/meta-python/recipes-devtools/python/ |
| H A D | python3-luma-oled_3.14.0.bb | 4 SSD1325, SSD1327, SSD1331, SSD1351 or SH1106 chipset"
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| /openbmc/u-boot/tools/binman/etype/ |
| H A D | intel_cmc.py | 12 """Entry containing an Intel Chipset Micro Code (CMC) file
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| /openbmc/phosphor-dbus-interfaces/yaml/com/intel/Control/ |
| H A D | NMISource.interface.yaml | 46 Via chipset NMI.
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| /openbmc/u-boot/arch/x86/include/asm/arch-quark/acpi/ |
| H A D | platform.asl | 34 /* Chipset specific sleep states */
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| /openbmc/u-boot/arch/x86/include/asm/arch-baytrail/acpi/ |
| H A D | platform.asl | 37 /* Chipset specific sleep states */
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| /openbmc/u-boot/arch/x86/cpu/qemu/ |
| H A D | qemu.c | 92 * i440FX and Q35 chipset have different PAM register offset, but with in qemu_chipset_init()
112 * Note: QEMU always decode legacy IDE I/O port on PIIX chipset. in qemu_chipset_init()
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| /openbmc/u-boot/board/ti/evm/ |
| H A D | evm.c | 55 * the Ethernet chipset. in omap3_evm_get_revision()
64 /* SMSC9115 chipset */ in omap3_evm_get_revision()
68 /* SMSC 9220 chipset */ in omap3_evm_get_revision()
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| /openbmc/bmcweb/redfish-core/include/generated/enums/ |
| H A D | log_entry.hpp | 114 ChipSet, enumerator
268 {SensorType::ChipSet, "ChipSet"},
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| /openbmc/u-boot/board/intel/cougarcanyon2/ |
| H A D | cougarcanyon2.c | 29 /* Initialize LPC interface to turn on superio chipset decode range */ in board_early_init_f()
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| /openbmc/qemu/hw/display/ |
| H A D | vga_regs.h | 2 * linux/include/video/vga.h -- standard VGA chipset interaction
28 /* Multi-chipset support Copyright 1993 Harm Hanemaayer */
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/ssiapi/ |
| H A D | ssiapi_1.3.0.bb | 4 … manage storage devices including creating and managing Raid arrays on systems with Intel chipset."
|