Home
last modified time | relevance | path

Searched full:channel (Results 1 – 25 of 4588) sorted by relevance

12345678910>>...184

/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/atsc/
H A Dus-Cable-Standard-center-frequencies-QAM2562 # Channels are in ascending EIA/NCTA channel designation order
5 [CHANNEL]
11 [CHANNEL]
17 [CHANNEL]
23 [CHANNEL]
29 [CHANNEL]
35 [CHANNEL]
41 [CHANNEL]
47 [CHANNEL]
54 [CHANNEL]
[all …]
H A Dus-Cable-IRC-center-frequencies-QAM2563 # Channels are in ascending EIA/NCTA channel designation order
6 [CHANNEL]
12 [CHANNEL]
18 [CHANNEL]
24 [CHANNEL]
30 [CHANNEL]
36 [CHANNEL]
42 [CHANNEL]
48 [CHANNEL]
54 [CHANNEL]
[all …]
H A Dus-Cable-HRC-center-frequencies-QAM2563 # Channels are in ascending EIA/NCTA channel designation order
6 [CHANNEL]
12 [CHANNEL]
18 [CHANNEL]
24 [CHANNEL]
30 [CHANNEL]
36 [CHANNEL]
42 [CHANNEL]
48 [CHANNEL]
54 [CHANNEL]
[all …]
H A Dus-Cable-EIA-542-HRC-center-frequencies-QAM2563 # Channels 1 to 125 are in ascending EIA/NCTA channel designation order
6 [CHANNEL]
12 [CHANNEL]
18 [CHANNEL]
24 [CHANNEL]
30 [CHANNEL]
36 [CHANNEL]
42 [CHANNEL]
48 [CHANNEL]
54 [CHANNEL]
[all …]
H A Dus-Cable-EIA-542-IRC-center_frequencies-QAM2563 # Channels 1-125 are in ascending EIA/NCTA channel designation order
6 [CHANNEL]
12 [CHANNEL]
18 [CHANNEL]
24 [CHANNEL]
30 [CHANNEL]
36 [CHANNEL]
42 [CHANNEL]
48 [CHANNEL]
54 [CHANNEL]
[all …]
H A Dus-NTSC-center-frequencies-8VSB3 [CHANNEL]
9 [CHANNEL]
15 [CHANNEL]
21 [CHANNEL]
27 [CHANNEL]
33 [CHANNEL]
39 [CHANNEL]
45 [CHANNEL]
51 [CHANNEL]
57 [CHANNEL]
[all …]
H A Dus-ATSC-center-frequencies-8VSB3 [CHANNEL]
9 [CHANNEL]
15 [CHANNEL]
21 [CHANNEL]
27 [CHANNEL]
33 [CHANNEL]
39 [CHANNEL]
45 [CHANNEL]
51 [CHANNEL]
57 [CHANNEL]
[all …]
/openbmc/linux/drivers/net/ethernet/sfc/
H A Defx_channels.c156 * We need a channel per event queue, plus a VI per tx queue. in efx_allocate_msix_channels()
273 /* Fall back to single channel MSI */ in efx_probe_interrupts()
366 struct efx_channel *channel; in efx_set_interrupt_affinity() local
374 efx_for_each_channel(channel, efx) { in efx_set_interrupt_affinity()
378 irq_set_affinity_hint(channel->irq, cpumask_of(cpu)); in efx_set_interrupt_affinity()
384 struct efx_channel *channel; in efx_clear_interrupt_affinity() local
386 efx_for_each_channel(channel, efx) in efx_clear_interrupt_affinity()
387 irq_set_affinity_hint(channel->irq, NULL); in efx_clear_interrupt_affinity()
403 struct efx_channel *channel; in efx_remove_interrupts() local
406 efx_for_each_channel(channel, efx) in efx_remove_interrupts()
[all …]
/openbmc/linux/drivers/net/ethernet/sfc/siena/
H A Defx_channels.c157 * We need a channel per event queue, plus a VI per tx queue. in efx_allocate_msix_channels()
274 /* Fall back to single channel MSI */ in efx_siena_probe_interrupts()
367 struct efx_channel *channel; in efx_siena_set_interrupt_affinity() local
375 efx_for_each_channel(channel, efx) { in efx_siena_set_interrupt_affinity()
379 irq_set_affinity_hint(channel->irq, cpumask_of(cpu)); in efx_siena_set_interrupt_affinity()
385 struct efx_channel *channel; in efx_siena_clear_interrupt_affinity() local
387 efx_for_each_channel(channel, efx) in efx_siena_clear_interrupt_affinity()
388 irq_set_affinity_hint(channel->irq, NULL); in efx_siena_clear_interrupt_affinity()
404 struct efx_channel *channel; in efx_siena_remove_interrupts() local
407 efx_for_each_channel(channel, efx) in efx_siena_remove_interrupts()
[all …]
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-s/
H A DNSS-806-40.5W4 [CHANNEL]
12 [CHANNEL]
20 [CHANNEL]
28 [CHANNEL]
36 [CHANNEL]
44 [CHANNEL]
52 [CHANNEL]
60 [CHANNEL]
68 [CHANNEL]
76 [CHANNEL]
[all …]
H A DHotbird-13.0E3 [CHANNEL]
11 [CHANNEL]
19 [CHANNEL]
27 [CHANNEL]
35 [CHANNEL]
43 [CHANNEL]
51 [CHANNEL]
59 [CHANNEL]
67 [CHANNEL]
75 [CHANNEL]
[all …]
H A DBrasilsatB4-84.0W4 [CHANNEL]
12 [CHANNEL]
20 [CHANNEL]
28 [CHANNEL]
36 [CHANNEL]
44 [CHANNEL]
52 [CHANNEL]
60 [CHANNEL]
68 [CHANNEL]
76 [CHANNEL]
[all …]
H A DTurksat-42.0E3 [CHANNEL]
11 [CHANNEL]
19 [CHANNEL]
27 [CHANNEL]
35 [CHANNEL]
43 [CHANNEL]
51 [CHANNEL]
59 [CHANNEL]
67 [CHANNEL]
75 [CHANNEL]
[all …]
H A DSatmex-5-116.8W4 [CHANNEL]
12 [CHANNEL]
20 [CHANNEL]
28 [CHANNEL]
36 [CHANNEL]
44 [CHANNEL]
52 [CHANNEL]
60 [CHANNEL]
68 [CHANNEL]
76 [CHANNEL]
[all …]
H A DGalaxy25-93.0W3 [CHANNEL]
11 [CHANNEL]
19 [CHANNEL]
27 [CHANNEL]
35 [CHANNEL]
43 [CHANNEL]
51 [CHANNEL]
59 [CHANNEL]
67 [CHANNEL]
75 [CHANNEL]
[all …]
H A DSirius-5.0E4 [CHANNEL]
12 [CHANNEL]
20 [CHANNEL]
28 [CHANNEL]
36 [CHANNEL]
44 [CHANNEL]
52 [CHANNEL]
60 [CHANNEL]
68 [CHANNEL]
76 [CHANNEL]
[all …]
H A DEutelsatW2-16E4 [CHANNEL]
12 [CHANNEL]
20 [CHANNEL]
28 [CHANNEL]
36 [CHANNEL]
44 [CHANNEL]
52 [CHANNEL]
60 [CHANNEL]
68 [CHANNEL]
76 [CHANNEL]
[all …]
H A DThor-1.0W3 [CHANNEL]
11 [CHANNEL]
19 [CHANNEL]
27 [CHANNEL]
35 [CHANNEL]
43 [CHANNEL]
51 [CHANNEL]
59 [CHANNEL]
67 [CHANNEL]
75 [CHANNEL]
[all …]
/openbmc/linux/drivers/rpmsg/
H A Dqcom_smd.c30 * Each channel consists of a control item (channel info) and a ring buffer
31 * pair. The channel info carry information related to channel state, flow
37 * Upon creating a new channel the remote processor allocates channel info and
39 * interrupt is sent to the other end of the channel and a scan for new
40 * channels should be done. A channel never goes away, it will only change
44 * channel by setting the state of its end of the channel to "opening" and
46 * consume the channel. Upon finding a consumer we finish the handshake and the
47 * channel is up.
49 * Upon closing a channel, the remote processor will update the state of its
50 * end of the channel and signal us, we will then unregister any attached
[all …]
/openbmc/linux/drivers/char/xillybus/
H A Dxillybus_core.c102 "Malformed message (skipping): opcode=%d, channel=%03x, dir=%d, bufno=%03x, data=%07x\n", in malformed_message()
120 struct xilly_channel *channel; in xillybus_isr() local
177 channel = ep->channels[msg_channel]; in xillybus_isr()
179 if (msg_dir) { /* Write channel */ in xillybus_isr()
180 if (msg_bufno >= channel->num_wr_buffers) { in xillybus_isr()
184 spin_lock(&channel->wr_spinlock); in xillybus_isr()
185 channel->wr_buffers[msg_bufno]->end_offset = in xillybus_isr()
187 channel->wr_fpga_buf_idx = msg_bufno; in xillybus_isr()
188 channel->wr_empty = 0; in xillybus_isr()
189 channel->wr_sleepy = 0; in xillybus_isr()
[all …]
/openbmc/linux/drivers/staging/greybus/
H A Dlight.c69 static void gb_lights_channel_free(struct gb_channel *channel);
71 static struct gb_connection *get_conn_from_channel(struct gb_channel *channel) in get_conn_from_channel() argument
73 return channel->light->glights->connection; in get_conn_from_channel()
81 static bool is_channel_flash(struct gb_channel *channel) in is_channel_flash() argument
83 return !!(channel->mode & (GB_CHANNEL_MODE_FLASH | GB_CHANNEL_MODE_TORCH in is_channel_flash()
95 static struct led_classdev *get_channel_cdev(struct gb_channel *channel) in get_channel_cdev() argument
97 return &channel->fled.led_cdev; in get_channel_cdev()
103 struct gb_channel *channel; in get_channel_from_mode() local
107 channel = &light->channels[i]; in get_channel_from_mode()
108 if (channel->mode == mode) in get_channel_from_mode()
[all …]
/openbmc/linux/drivers/ipack/devices/
H A Dipoctal.c48 struct ipoctal_channel channel[NR_CHANNELS]; member
57 return container_of(chan, struct ipoctal, channel[index]); in chan_to_ipoctal()
60 static void ipoctal_reset_channel(struct ipoctal_channel *channel) in ipoctal_reset_channel() argument
62 iowrite8(CR_DISABLE_RX | CR_DISABLE_TX, &channel->regs->w.cr); in ipoctal_reset_channel()
63 channel->rx_enable = 0; in ipoctal_reset_channel()
64 iowrite8(CR_CMD_RESET_RX, &channel->regs->w.cr); in ipoctal_reset_channel()
65 iowrite8(CR_CMD_RESET_TX, &channel->regs->w.cr); in ipoctal_reset_channel()
66 iowrite8(CR_CMD_RESET_ERR_STATUS, &channel->regs->w.cr); in ipoctal_reset_channel()
67 iowrite8(CR_CMD_RESET_MR, &channel->regs->w.cr); in ipoctal_reset_channel()
72 struct ipoctal_channel *channel; in ipoctal_port_activate() local
[all …]
/openbmc/linux/drivers/phy/renesas/
H A Dr8a779f0-ether-serdes.c37 struct r8a779f0_eth_serdes_channel channel[R8A779F0_ETH_SERDES_NUM]; member
53 r8a779f0_eth_serdes_reg_wait(struct r8a779f0_eth_serdes_channel *channel, in r8a779f0_eth_serdes_reg_wait() argument
59 iowrite32(bank, channel->addr + R8A779F0_ETH_SERDES_BANK_SELECT); in r8a779f0_eth_serdes_reg_wait()
61 ret = readl_poll_timeout_atomic(channel->addr + offs, val, in r8a779f0_eth_serdes_reg_wait()
65 dev_dbg(&channel->phy->dev, in r8a779f0_eth_serdes_reg_wait()
67 __func__, channel->index, offs, bank, mask, expected); in r8a779f0_eth_serdes_reg_wait()
75 struct r8a779f0_eth_serdes_channel *channel; in r8a779f0_eth_serdes_common_init_ram() local
79 channel = &dd->channel[i]; in r8a779f0_eth_serdes_common_init_ram()
80 ret = r8a779f0_eth_serdes_reg_wait(channel, 0x026c, 0x180, BIT(0), 0x01); in r8a779f0_eth_serdes_common_init_ram()
91 r8a779f0_eth_serdes_common_setting(struct r8a779f0_eth_serdes_channel *channel) in r8a779f0_eth_serdes_common_setting() argument
[all …]
/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddma.txt4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
24 - interrupts : interrupt specifier for DMA channel IRQ
38 dma-channel@0 {
39 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
45 dma-channel@80 {
46 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
[all …]
/openbmc/linux/drivers/dma/sh/
H A Drz-dmac.c192 static void rz_dmac_ch_writel(struct rz_dmac_chan *channel, unsigned int val, in rz_dmac_ch_writel() argument
196 writel(val, channel->ch_base + offset); in rz_dmac_ch_writel()
198 writel(val, channel->ch_cmn_base + offset); in rz_dmac_ch_writel()
201 static u32 rz_dmac_ch_readl(struct rz_dmac_chan *channel, in rz_dmac_ch_readl() argument
205 return readl(channel->ch_base + offset); in rz_dmac_ch_readl()
207 return readl(channel->ch_cmn_base + offset); in rz_dmac_ch_readl()
215 static void rz_lmdesc_setup(struct rz_dmac_chan *channel, in rz_lmdesc_setup() argument
220 channel->lmdesc.base = lmdesc; in rz_lmdesc_setup()
221 channel->lmdesc.head = lmdesc; in rz_lmdesc_setup()
222 channel->lmdesc.tail = lmdesc; in rz_lmdesc_setup()
[all …]

12345678910>>...184