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Searched full:clk_div_gdr (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dexynos4.h239 #define CLK_DIV_GDR 460 macro
H A Dexynos3250.h86 #define CLK_DIV_GDR 67 macro
/openbmc/linux/Documentation/devicetree/bindings/interconnect/
H A Dsamsung,exynos-bus.yaml280 clocks = <&cmu CLK_DIV_GDR>;
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos4210.dtsi170 clocks = <&clock CLK_DIV_GDR>;
H A Dexynos4x12.dtsi153 clocks = <&clock CLK_DIV_GDR>;
H A Dexynos3250.dtsi191 clocks = <&cmu CLK_DIV_GDR>;
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos3250.c346 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
H A Dclk-exynos4.c599 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),