| /openbmc/linux/arch/arm64/kvm/hyp/nvhe/ |
| H A D | sys_regs.c | 260 * Accessor for AArch32 feature id registers.
262 * The value of these registers is "unknown" according to the spec if AArch32
275 * No support for AArch32 guests, therefore, pKVM has no sanitized copy in pvm_access_id_aarch32()
276 * of AArch32 feature id registers. in pvm_access_id_aarch32()
315 /* Mark the specified system register as an AArch32 feature id register. */
316 #define AARCH32(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch32 } macro
349 /* AArch64 mappings of the AArch32 ID registers */
351 AARCH32(SYS_ID_PFR0_EL1),
352 AARCH32(SYS_ID_PFR1_EL1),
353 AARCH32(SYS_ID_DFR0_EL1),
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| /openbmc/qemu/docs/system/arm/ |
| H A D | emulation.rst | 10 - FEAT_AA32BF16 (AArch32 BFloat16 instructions)
11 - FEAT_AA32EL0 (Support for AArch32 at EL0)
12 - FEAT_AA32EL1 (Support for AArch32 at EL1)
13 - FEAT_AA32EL2 (Support for AArch32 at EL2)
14 - FEAT_AA32EL3 (Support for AArch32 at EL3)
15 - FEAT_AA32HPD (AArch32 hierarchical permission disables)
16 - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
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| /openbmc/u-boot/arch/arm/mach-bcm283x/ |
| H A D | Kconfig | 60 This option creates a build targeting the ARMv7/AArch32 ISA.
83 This option creates a build targeting the ARMv7/AArch32 ISA.
90 the RPi 3 model B, in AArch32 (32-bit) mode.
99 This option creates a build targeting the ARMv7/AArch32 ISA.
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| /openbmc/libcper/include/libcper/sections/ |
| H A D | cper-section-arm.h | 81 (const char *[]){ "AArch32 General Purpose Registers", \
82 "AArch32 EL1 Context Registers", \
83 "AArch32 EL2 Context Registers", \
84 "AArch32 Secure Context Registers", \
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| /openbmc/linux/arch/arm64/include/asm/ |
| H A D | ptrace.h | 58 /* AArch32-specific ptrace requests */
68 /* SPSR_ELx bits for exceptions taken from AArch32 */
100 /* AArch32 CPSR bits, as seen in AArch32 */
124 /* sizeof(struct user) for AArch32 */
127 /* Architecturally defined mapping between AArch32 and AArch64 registers */
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| H A D | kvm_emulate.h | 178 * AArch32 with banked registers.
250 * The layout of SPSR for an AArch32 state is different when observed from an
251 * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32
257 * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256
258 * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280
265 * | 21 | SS | DIT | SS doesn't exist in AArch32 |
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| H A D | elf.h | 209 /* AArch32 registers. */
214 /* AArch32 EABI. */
264 /* No known properties for AArch32 yet */ in arch_parse_elf_property()
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| /openbmc/linux/arch/arm64/kvm/hyp/ |
| H A D | exception.c | 82 * of the inherited bits have the same position in the AArch64/AArch32 SPSR_ELx
83 * layouts, so we don't need to shuffle these for exceptions from AArch32 EL0.
86 * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426.
182 * For the SPSR layout seen from AArch32, see:
186 * For the SPSR_ELx layout for AArch32 seen from AArch64, see:
189 * Here we manipulate the fields in order of the AArch32 SPSR_ELx layout, from
224 // SS does not exist in AArch32, so ignore in get_except32_cpsr()
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| /openbmc/qemu/.gitlab-ci.d/custom-runners/ |
| H A D | ubuntu-22.04-aarch32.yml | 5 ubuntu-22.04-aarch32-all:
11 - aarch32
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| /openbmc/u-boot/arch/arm/include/asm/ |
| H A D | macro.h | 179 /* Check switch to AArch64 EL2 or AArch32 Hypervisor mode */
212 * The next lower exception level is AArch32, 32bit EL2 | HCE |
220 /* Return to AArch32 Hypervisor mode */
286 /* Check switch to AArch64 EL1 or AArch32 Supervisor mode */
307 /* Return to AArch32 Supervisor mode from EL2 */
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| /openbmc/libcper/generator/sections/ |
| H A D | gen-section-arm.c | 170 //AARCH32 GPR, AARCH32 EL2 in generate_arm_context_info()
176 //AARCH32 EL1 in generate_arm_context_info()
181 //AARCH32 EL3 in generate_arm_context_info()
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| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/ |
| H A D | instruction.json | 13 …"PublicDescription": "This event only counts writes to CONTEXTIDR in AArch32 state, and via the CO…
20 …"PublicDescription": "This event only counts writes to TTBR0/TTBR1 in AArch32 state and TTBR0_EL1/…
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| /openbmc/u-boot/arch/arm/cpu/armv8/ |
| H A D | psci.S | 292 b unhandled_exception /* Sync, Lower EL using AArch32 */
294 b unhandled_exception /* IRQ, Lower EL using AArch32 */
296 b unhandled_exception /* FIQ, Lower EL using AArch32 */
298 b unhandled_exception /* SError, Lower EL using AArch32 */
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| /openbmc/qemu/target/arm/ |
| H A D | arm-powerctl.c | 106 "\n", cpuid, target_el, target_aa64 ? "aarch64" : "aarch32", entry, in arm_set_cpu_on()
137 * "target_el" and be in the requested mode (AArch64 or AArch32). in arm_set_cpu_on()
150 * For now we don't support booting an AArch64 CPU in AArch32 mode in arm_set_cpu_on()
155 " in AArch32 mode is not supported yet\n", in arm_set_cpu_on()
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| H A D | syndrome.h | 108 * few cases the value in HSR for exceptions taken to AArch32 Hyp
112 * when taking an exception to AArch32. For those we include the extra coproc
214 /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */ in syn_fp_access_trap()
222 /* AArch32 SIMD trap: TA == 1 coproc == 0 */ in syn_simd_access_trap()
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| H A D | cpu.h | 88 /* The usual mapping for an AArch64 system register to its AArch32
152 * differs between AArch64 and AArch32.
153 * In AArch32:
184 /* In AArch32 mode, predicate registers do not exist at all. */
189 /* In AArch32 mode, PAC keys do not exist at all. */
222 * semantics as for AArch32, as described in the comments on each field)
581 uint32_t fsr; /* AArch32 format fault status register info */
1312 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
1315 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
1333 #define SCTLR_V (1U << 13) /* AArch32 only */
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | rmr_switch.S | 4 @ All 64-bit capable Allwinner SoCs reset in AArch32 (and continue to
9 @ into a different execution state (AArch32 or AArch64).
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| /openbmc/qemu/include/hw/xen/interface/ |
| H A D | arch-arm.h | 170 * hypercall argument. It is 4 bytes on aarch32 and 8 bytes on aarch64.
214 /* Aarch64 Aarch32 */
261 uint32_t spsr_svc; /* AArch32 */
264 /* AArch32 guests only */
361 #define PSR_MODE_BIT 0x10 /* Set iff AArch32 */
376 * zImage kernels on aarch32.
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| /openbmc/linux/Documentation/trace/coresight/ |
| H A D | coresight-cpu-debug.rst | 43 - The driver supports a CPU running in either AArch64 or AArch32 mode. The
45 'ED' for register prefix (ARM DDI 0487A.k, chapter H9.1) and AArch32 uses
60 no offset applied and do not sample the instruction set state in AArch32
62 in AArch32 state, EDPCSR is not sampled; when the CPU operates in AArch64
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| /openbmc/linux/arch/arm64/kernel/ |
| H A D | kuser32.S | 3 * AArch32 user helpers.
11 * reasons with 32 bit (aarch32) applications that need them.
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| /openbmc/linux/drivers/firmware/efi/ |
| H A D | cper-arm.c | 21 "AArch32 general purpose registers",
22 "AArch32 EL1 context registers",
23 "AArch32 EL2 context registers",
24 "AArch32 secure context registers",
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| /openbmc/u-boot/board/sunxi/ |
| H A D | README.sunxi64 | 5 both the 64-bit AArch64 mode and the ARMv7 compatible 32-bit AArch32 mode.
8 These SoCs are wired to start in AArch32 mode on reset and execute 32-bit
59 enters the SPL still in AArch32 secure SVC mode, there is some shim code to
102 AArch32. For now the AArch64 SPL cannot properly return into FEL mode, so the
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| /openbmc/linux/lib/raid6/ |
| H A D | recov_neon_inner.c | 12 * AArch32 does not provide this intrinsic natively because it does not
13 * implement the underlying instruction. AArch32 only provides a 64-bit
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| /openbmc/openbmc/meta-arm/meta-arm/recipes-bsp/trusted-firmware-a/ |
| H A D | trusted-firmware-a_%.bbappend | 5 # arm/aarch32. This is a known testing hole in TF-A.
49 ARCH=aarch32 \
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| /openbmc/linux/arch/arm64/kvm/hyp/include/nvhe/ |
| H A D | fixed_config.h | 48 * - AArch64 guests only (no support for AArch32 guests):
49 * AArch32 adds complexity in trap handling, emulation, condition codes,
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