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/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-t/
H A Dcz-All2 # Created from http://www.ctu.cz/cs/download/plan-vyuziti-radioveho-spektra/rok_2012/pv-p_10-08_201…
4 [CHANNEL]
11 TRANSMISSION_MODE = 8K
12 GUARD_INTERVAL = 1/8
16 [CHANNEL]
23 TRANSMISSION_MODE = 8K
24 GUARD_INTERVAL = 1/8
28 [CHANNEL]
35 TRANSMISSION_MODE = 8K
36 GUARD_INTERVAL = 1/8
[all …]
H A Dit-All1 # This file lists all frequencies used in Western Europe for DVB-T.
4 # Moreover, other countries use a bandwidth of 8 MHz also for Band III
16 ### VHF - Band III ###
18 [CHANNEL]
25 TRANSMISSION_MODE = 8K
31 [CHANNEL]
38 TRANSMISSION_MODE = 8K
44 [CHANNEL]
51 TRANSMISSION_MODE = 8K
56 # 8
[all …]
H A Dnl-All2 # Created from http://radio-tv-nederland.nl/TV 1.251978e-312nderlijst%20Nederland.xls
3 # and http://radio-tv-nederland.nl/dvbt/dvbt-lokaal.html
4 [CHANNEL]
11 TRANSMISSION_MODE = 8K
16 [CHANNEL]
23 TRANSMISSION_MODE = 8K
28 [CHANNEL]
35 TRANSMISSION_MODE = 8K
40 [CHANNEL]
47 TRANSMISSION_MODE = 8K
[all …]
H A Dch-Citycable1 # Lausanne - Switzerland (DVB-T on CityCable cable network)
2 [CHANNEL]
6 CODE_RATE_HP = 7/8
9 TRANSMISSION_MODE = 8K
14 [CHANNEL]
18 CODE_RATE_HP = 7/8
21 TRANSMISSION_MODE = 8K
26 [CHANNEL]
30 CODE_RATE_HP = 7/8
33 TRANSMISSION_MODE = 8K
[all …]
H A Dat-All1 # Austria, all DVB-T transmitters run by ORS
3 # http://www.ors.at/fileadmin/user_upload/downloads/DVB-T_Kanalbezeichnungen_und_Mittenfrequenzen.p…
4 [CHANNEL]
11 TRANSMISSION_MODE = 8K
16 [CHANNEL]
23 TRANSMISSION_MODE = 8K
28 [CHANNEL]
35 TRANSMISSION_MODE = 8K
40 [CHANNEL]
47 TRANSMISSION_MODE = 8K
[all …]
H A Dee-All3 # and http://wiki.wifi.ee/index.php/DVB-T#Tehniline_teave
5 [CHANNEL]
12 TRANSMISSION_MODE = 8K
13 GUARD_INTERVAL = 1/8
17 [CHANNEL]
24 TRANSMISSION_MODE = 8K
25 GUARD_INTERVAL = 1/8
29 [CHANNEL]
36 TRANSMISSION_MODE = 8K
37 GUARD_INTERVAL = 1/8
[all …]
H A Ddk-All2 # Created from http://www.digi-tv.dk/Indhold_og_tilbud/frekvenser.asp
3 # and http://www.digi-tv.dk/Sendenettets_opbygning/
4 [CHANNEL]
11 TRANSMISSION_MODE = 8K
16 [CHANNEL]
23 TRANSMISSION_MODE = 8K
28 [CHANNEL]
35 TRANSMISSION_MODE = 8K
40 [CHANNEL]
47 TRANSMISSION_MODE = 8K
[all …]
H A Dch-Geneva3 #------------------------------------------------------------------------------
4 [CHANNEL]
11 TRANSMISSION_MODE = 8K
16 [CHANNEL]
23 TRANSMISSION_MODE = 8K
28 [CHANNEL]
35 TRANSMISSION_MODE = 8K
36 GUARD_INTERVAL = 1/8
40 [CHANNEL]
47 TRANSMISSION_MODE = 8K
[all …]
H A Des-Donostia1 # The channels with 1/32 guard-interval are French and should be perfectly visible
2 # here. However I have only managed to get a lock for the channel 57 of the French ones.
3 [CHANNEL]
10 TRANSMISSION_MODE = 8K
15 [CHANNEL]
22 TRANSMISSION_MODE = 8K
27 [CHANNEL]
34 TRANSMISSION_MODE = 8K
39 [CHANNEL]
46 TRANSMISSION_MODE = 8K
[all …]
H A Dse-Vasteras_Lillharad1 # Sweden - Västerås/Lillhärad
2 [CHANNEL]
9 TRANSMISSION_MODE = 8K
10 GUARD_INTERVAL = 1/8
14 [CHANNEL]
21 TRANSMISSION_MODE = 8K
22 GUARD_INTERVAL = 1/8
26 [CHANNEL]
33 TRANSMISSION_MODE = 8K
34 GUARD_INTERVAL = 1/8
[all …]
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-s/
H A DAnik-F3-119W1 #Dish Network USA works with PSK/8turbo
2 #Just DVBS-USB Genpix Sky Walker 1 or 2 works with PSK/8turbo
4 [CHANNEL]
10 MODULATION = PSK/8
13 [CHANNEL]
19 MODULATION = PSK/8
22 [CHANNEL]
28 MODULATION = PSK/8
31 [CHANNEL]
37 MODULATION = PSK/8
[all …]
H A DEchostar-10+11-110W1 #Dish Network USA works with PSK/8turbo
2 #Just DVBS-USB Genpix Sky Walker 1 or 2 works with PSK/8turbo
4 [CHANNEL]
10 MODULATION = PSK/8
13 [CHANNEL]
19 MODULATION = PSK/8
22 [CHANNEL]
28 MODULATION = PSK/8
31 [CHANNEL]
40 [CHANNEL]
[all …]
H A DIntelsat34_C-55.5W1 # Intelsat 34 @ 55.5W C-BAND
4 [CHANNEL]
13 [CHANNEL]
22 [CHANNEL]
31 [CHANNEL]
40 [CHANNEL]
49 [CHANNEL]
58 [CHANNEL]
64 MODULATION = PSK/8
67 [CHANNEL]
[all …]
H A DIntelsat21_C-58.0W1 # Intelsat 21 @ 58.0W C-BAND
4 [CHANNEL]
10 MODULATION = PSK/8
13 [CHANNEL]
19 MODULATION = PSK/8
22 [CHANNEL]
31 [CHANNEL]
40 [CHANNEL]
45 INNER_FEC = 7/8
49 [CHANNEL]
[all …]
H A DGalaxy19_C-97.0W1 # Galaxy 19 @ 97W C-BAND
3 [CHANNEL]
9 MODULATION = PSK/8
12 [CHANNEL]
21 [CHANNEL]
27 MODULATION = PSK/8
30 [CHANNEL]
36 MODULATION = PSK/8
39 [CHANNEL]
48 [CHANNEL]
[all …]
H A DGalaxy23_C-121W1 # Galaxy 23 @ 121W C-BAND
4 [CHANNEL]
10 MODULATION = PSK/8
13 [CHANNEL]
22 [CHANNEL]
31 [CHANNEL]
37 MODULATION = PSK/8
40 [CHANNEL]
49 [CHANNEL]
54 INNER_FEC = 7/8
[all …]
H A DGalaxy16_C-99.0W1 # Galaxy 16 @ 99W C-BAND
3 [CHANNEL]
9 MODULATION = PSK/8
12 [CHANNEL]
21 [CHANNEL]
30 [CHANNEL]
39 [CHANNEL]
48 [CHANNEL]
57 [CHANNEL]
62 INNER_FEC = 7/8
[all …]
/openbmc/linux/include/sound/
H A Dump_msg.h1 // SPDX-License-Identifier: GPL-2.0-or-later
27 /* MIDI 1.0 Channel Control (7bit) */
36 UMP_CC_BALANCE = 8,
134 u32 channel:4; member
135 u32 note:8;
136 u32 velocity:8;
138 u32 velocity:8;
139 u32 note:8;
140 u32 channel:4;
153 u32 channel:4; member
[all …]
/openbmc/linux/sound/core/oss/
H A Dlinear.c2 * Linear conversion Plug-In
4 * Abramo Bagnara <abramo@alsa-project.org>
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
48 memcpy(p + data->copy_ofs, src + data->src_ofs, data->copy_bytes); in do_convert()
49 if (data->cvt_endian) in do_convert()
51 tmp ^= data->flip; in do_convert()
52 memcpy(dst, p + data->dst_ofs, data->dst_bytes); in do_convert()
60 struct linear_priv *data = (struct linear_priv *)plugin->extra_data; in convert()
61 int channel; in convert() local
62 int nchannels = plugin->src_format.channels; in convert()
[all …]
H A Drate.c2 * Rate conversion Plug-In
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #define R_MASK (BITS-1)
55 unsigned int channel; in rate_init() local
56 struct rate_priv *data = (struct rate_priv *)plugin->extra_data; in rate_init()
57 data->pos = 0; in rate_init()
58 for (channel = 0; channel < plugin->src_format.channels; channel++) { in rate_init()
59 data->channels[channel].last_S1 = 0; in rate_init()
60 data->channels[channel].last_S2 = 0; in rate_init()
73 unsigned int channel; in resample_expand() local
[all …]
H A Dmulaw.c2 * Mu-Law conversion Plug-In Interface
4 * Uros Bizjak <uros@kss-loka.si>
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #define SIGN_BIT (0x80) /* Sign bit for a u-law byte. */
31 #define NSEGS (8) /* Number of u-law segments. */
55 * linear2ulaw() - Convert a linear PCM value to u-law
58 * is biased by adding 33 which shifts the encoding range from (0 - 8158) to
59 * (33 - 8191). The result can be seen in the following encoding table:
62 * ------------------------ ---------------
75 * four bits wxyz. * The trailing bits (a - h) are ignored.
[all …]
/openbmc/linux/drivers/clk/bcm/
H A Dclk-ns2.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-ns2.h>
12 #include "clk-iproc.h"
49 .channel = BCM_NS2_GENPLL_SCR_SCR_CLK,
52 .mdiv = REG_VAL(0x18, 0, 8),
55 .channel = BCM_NS2_GENPLL_SCR_FS_CLK,
58 .mdiv = REG_VAL(0x18, 8, 8),
61 .channel = BCM_NS2_GENPLL_SCR_AUDIO_CLK,
64 .mdiv = REG_VAL(0x14, 0, 8),
[all …]
/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddma.txt4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
[all …]
/openbmc/linux/sound/soc/sprd/
H A Dsprd-mcdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
57 /* Channel water mark definition */
60 #define MCDT_CH_FIFO_AF_MASK GENMASK(8, 0)
62 /* DMA channel select definition */
67 #define MCDT_DMA_CH2_SEL_MASK GENMASK(11, 8)
68 #define MCDT_DMA_CH2_SEL_SHIFT 8
75 /* DMA channel ACK select definition */
78 /* Channel FIFO definition */
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
[all …]
/openbmc/linux/drivers/hsi/controllers/
H A Domap_ssi_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
32 #define SSI_MPU_ENABLE_REG(port, irq) (0x80c + ((port) * 0x10) + ((irq) * 8))
33 # define SSI_DATAACCEPT(channel) (1 << (channel)) argument
34 # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) argument
35 # define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16)) argument
40 # define SSI_GDD_LCH(channel) (1 << (channel)) argument
44 # define SSI_WAKE(channel) (1 << (channel)) argument
57 #define SSI_SST_FRAMESIZE_REG 8
62 # define SSI_FULL(channel) (1 << (channel)) argument
71 #define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) argument
[all …]

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