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/openbmc/u-boot/board/freescale/b4860qds/
H A Db4860qds_crossbar_con.h1 /* SPDX-License-Identifier: GPL-2.0+ */
9 #define NUM_CON_VSC3316 8
10 #define NUM_CON_VSC3308 4
12 static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
13 {5, 11}, {4, 5}, {2, 6}, {12, 9} };
15 static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
16 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
18 static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
19 {7, 8}, {9, 0}, {2, 14}, {12, 15},
20 {-1, -1}, {-1, -1} };
[all …]
/openbmc/u-boot/include/
H A Dipu_pixfmt.h1 /* SPDX-License-Identifier: GPL-2.0+ */
8 * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
19 (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
29 #define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8')
31 #define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*< 8 RGB-3-3-2 */
32 #define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*< 16 RGB-5-5-5 */
33 #define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*< 1 6 RGB-5-6-5 */
34 #define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*< 18 RGB-6-6-6 */
35 #define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*< 18 BGR-6-6-6 */
36 #define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*< 24 BGR-8-8-8 */
[all …]
/openbmc/u-boot/drivers/sound/
H A Drt5677.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * rt5677.h -- RealTek ALC5677 ALSA SoC Audio driver
27 /* I/O - Output */
29 /* I/O - Input */
32 /* I/O - SLIMBus */
38 /* I/O - ADC/DAC */
50 /* Mixer - D-D */
67 /* Mixer - PDM */
123 /* Format - ADC/DAC */
131 /* Function - Analog */
[all …]
/openbmc/qemu/linux-user/hppa/
H A Dvdso.S6 * SPDX-License-Identifier: GPL-2.0-or-later
10 #include "vdso-asmoffset.h"
18 * a 64-byte boundary by 0, 4 or 5 instructions. Since the vdso trampoline
28 /* arch/parisc/kernel/asm-offsets.c */
30 (offsetof_sigcontext - PARISC_RT_SIGFRAME_SIZE32)
54 .cfi_def_cfa 30, -PARISC_RT_SIGFRAME_SIZE32 + offsetof_sigcontext
57 .cfi_offset 1, offsetof_sigcontext_gr + 1 * 4
58 .cfi_offset 2, offsetof_sigcontext_gr + 2 * 4
59 .cfi_offset 3, offsetof_sigcontext_gr + 3 * 4
60 .cfi_offset 4, offsetof_sigcontext_gr + 4 * 4
[all …]
/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_windowed.S26 movi a2, 1 | (((1 << ((\window) / 4)) | 1) << ((\shift) / 4))
43 movi a3, (\shift) / 4
54 movi a3, 1 | ((1 << ((\window) / 4)) << ((\shift) / 4))
63 overflow_test \shift, \window, %((\shift) - 1), \probe
69 .irp shift, 4, 8, 12
70 .irp window, 4, 8, 12
94 movi a3, (\window) / 4
110 movi a3, (XCHAL_NUM_AREGS - (\window)) / 4
123 assert bsi.l, a2, (XCHAL_NUM_AREGS - (\window)) / 4
131 underflow_test 4
[all …]
/openbmc/openbmc/meta-facebook/meta-ventura/recipes-phosphor/sensors/phosphor-virtual-sensor/
H A Dvirtual_sensor_config.json107 "MinValue": -127
163 "var CAL_OFS[11]:={-1.0, -1.0, -1.0, -1.5, -1.5, -2.5, -2.5, -3.0, -3.0, -3.0, -3.0};",
165 …AVG,DUTY_OFS[0]): SCM_TEMP_C+(CAL_OFS[0]+((DUTY_AVG-DUTY_OFS[0])*(CAL_OFS[1]-CAL_OFS[0])/(DUTY_OFS…
166 …AVG,DUTY_OFS[1]): SCM_TEMP_C+(CAL_OFS[1]+((DUTY_AVG-DUTY_OFS[1])*(CAL_OFS[2]-CAL_OFS[1])/(DUTY_OFS…
167 …AVG,DUTY_OFS[2]): SCM_TEMP_C+(CAL_OFS[2]+((DUTY_AVG-DUTY_OFS[2])*(CAL_OFS[3]-CAL_OFS[2])/(DUTY_OFS…
168 …ase inrange(DUTY_OFS[4],DUTY_AVG,DUTY_OFS[3]): SCM_TEMP_C+(CAL_OFS[3]+((DUTY_AVG-DUTY_OFS[3])*(CAL…
169 …Y_OFS[5],DUTY_AVG,DUTY_OFS[4]): SCM_TEMP_C+(CAL_OFS[4]+((DUTY_AVG-DUTY_OFS[4])*(CAL_OFS[5]-CAL_OFS…
170 …AVG,DUTY_OFS[5]): SCM_TEMP_C+(CAL_OFS[5]+((DUTY_AVG-DUTY_OFS[5])*(CAL_OFS[6]-CAL_OFS[5])/(DUTY_OFS…
171 …AVG,DUTY_OFS[6]): SCM_TEMP_C+(CAL_OFS[6]+((DUTY_AVG-DUTY_OFS[6])*(CAL_OFS[7]-CAL_OFS[6])/(DUTY_OFS…
172 …ase inrange(DUTY_OFS[8],DUTY_AVG,DUTY_OFS[7]): SCM_TEMP_C+(CAL_OFS[7]+((DUTY_AVG-DUTY_OFS[7])*(CAL…
[all …]
/openbmc/u-boot/arch/xtensa/cpu/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2008 - 2013 Tensilica Inc.
4 * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
12 #include <asm-offsets.h>
20 #define PT_PS 4
21 #define PT_DEPC 8
22 #define PT_EXCCAUSE 12
60 .align 4
72 * that DDR has been set up before running U-Boot. (See also comments
78 .align 4
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Dhw_data.c1 // SPDX-License-Identifier: GPL-2.0+
36 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
40 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
41 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
42 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
43 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
44 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
45 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
46 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
50 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
[all …]
/openbmc/u-boot/arch/arm/mach-davinci/
H A Dda850_pinmux.c1 // SPDX-License-Identifier: GPL-2.0+
21 { pinmux(4), 1, 1 }, /* SPI0_SCS[0] */
26 { pinmux(5), 1, 4 }, /* SPI1_SOMI */
36 { pinmux(3), 2, 4 }, /* UART0_RXD */
46 { pinmux(4), 2, 6 }, /* UART1_RXD */
47 { pinmux(4), 2, 7 }, /* UART1_TXD */
51 { pinmux(4), 2, 4 }, /* UART2_RXD */
52 { pinmux(4), 2, 5 }, /* UART2_TXD */
56 { pinmux(0), 4, 6 }, /* UART2_RTS */
57 { pinmux(0), 4, 7 }, /* UART2_CTS */
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dda8xx_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <dt-bindings/gpio/gpio.h>
28 #define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
32 { pinmux(13), 8, 6 }, /* GP0[0] */
33 { pinmux(13), 8, 7 },
34 { pinmux(14), 8, 0 },
35 { pinmux(14), 8, 1 },
36 { pinmux(14), 8, 2 },
37 { pinmux(14), 8, 3 },
38 { pinmux(14), 8, 4 },
[all …]
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage_128M16_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
[all …]
H A Dkwbimage_256M8_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
10 # This configuration applies to COGE5 design (ARM-part)
11 # Two 8-Bit devices are connected on the 16-Bit bus on the same
12 # chip-select. The supported devices are
13 # MT47H256M8EB-3IT:C
14 # MT47H256M8EB-25EIT:C
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
[all …]
H A Dkwbimage-memphis.cfg1 # SPDX-License-Identifier: GPL-2.0+
8 # Refer doc/README.kwbimage for more details about how-to configure
16 # bit 3-0: MPPSel0 2, NF_IO[2]
17 # bit 7-4: MPPSel1 2, NF_IO[3]
18 # bit 12-8: MPPSel2 2, NF_IO[4]
19 # bit 15-12: MPPSel3 2, NF_IO[5]
20 # bit 19-16: MPPSel4 1, NF_IO[6]
21 # bit 23-20: MPPSel5 1, NF_IO[7]
22 # bit 27-24: MPPSel6 1, SYSRST_O
23 # bit 31-28: MPPSel7 0, GPO[7]
[all …]
/openbmc/openbmc/meta-facebook/meta-santabarbara/recipes-phosphor/sensors/phosphor-virtual-sensor/
H A Dvirtual_sensor_config.json7 "MinValue": -127
34 …(CURR[0],PDB1_BTP1_CURR,CURR[1]): TEMP[0]+((PDB1_BTP1_CURR-CURR[0])*(TEMP[1]-TEMP[0])/(CURR[1]-CUR…
35 …(CURR[1],PDB1_BTP1_CURR,CURR[2]): TEMP[1]+((PDB1_BTP1_CURR-CURR[1])*(TEMP[2]-TEMP[1])/(CURR[2]-CUR…
36 …(CURR[2],PDB1_BTP1_CURR,CURR[3]): TEMP[2]+((PDB1_BTP1_CURR-CURR[2])*(TEMP[3]-TEMP[2])/(CURR[3]-CUR…
37 … case inrange(CURR[3],PDB1_BTP1_CURR,CURR[4]): TEMP[3]+((PDB1_BTP1_CURR-CURR[3])*(TEMP[4]-TEMP[3]…
38 …" case inrange(CURR[4],PDB1_BTP1_CURR,CURR[5]): TEMP[4]+((PDB1_BTP1_CURR-CURR[4])*(TEMP[5]-TEMP[4…
39 …(CURR[5],PDB1_BTP1_CURR,CURR[6]): TEMP[5]+((PDB1_BTP1_CURR-CURR[5])*(TEMP[6]-TEMP[5])/(CURR[6]-CUR…
40 …(CURR[6],PDB1_BTP1_CURR,CURR[7]): TEMP[6]+((PDB1_BTP1_CURR-CURR[6])*(TEMP[7]-TEMP[6])/(CURR[7]-CUR…
41 … case inrange(CURR[7],PDB1_BTP1_CURR,CURR[8]): TEMP[7]+((PDB1_BTP1_CURR-CURR[7])*(TEMP[8]-TEMP[7]…
42 …" case inrange(CURR[8],PDB1_BTP1_CURR,CURR[9]): TEMP[8]+((PDB1_BTP1_CURR-CURR[8])*(TEMP[9]-TEMP[8…
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
23 #define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(12)
27 #define ICPU_GENERAL_CTRL_IF_PI_SLV_DONEPOL BIT(8)
30 #define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4))
31 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(5, 4)
32 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4)
44 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
45 #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
50 #define ICPU_SW_MODE_SW_SPI_SCK BIT(12)
54 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
[all …]
/openbmc/qemu/hw/misc/
H A Dbcm2835_property.c5 * See the COPYING file in the top-level directory.
11 #include "hw/qdev-properties.h"
15 #include "hw/arm/raspberrypi-fw-defs.h"
24 /* https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface */
35 BCM2835FBConfig fbconfig = s->fbdev->config; in bcm2835_property_mbox_push()
40 s->addr = value; in bcm2835_property_mbox_push()
42 tot_len = ldl_le_phys(&s->dma_as, value); in bcm2835_property_mbox_push()
44 /* @(addr + 4) : Buffer response code */ in bcm2835_property_mbox_push()
45 value = s->addr + 8; in bcm2835_property_mbox_push()
46 while (value + 8 <= s->addr + tot_len) { in bcm2835_property_mbox_push()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mxs/
H A Dregs-lradc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
9 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
15 #include <asm/mach-imx/regs-common.h>
75 #define LRADC_CTRL1_BUTTON1_DETECT_IRQ (1 << 12)
79 #define LRADC_CTRL1_TOUCH_DETECT_IRQ (1 << 8)
83 #define LRADC_CTRL1_LRADC4_IRQ (1 << 4)
94 #define LRADC_CTRL2_DISABLE_MUXAMP_BYPASS (1 << 12)
96 #define LRADC_CTRL2_TEMP_SENSOR_IENABLE0 (1 << 8)
97 #define LRADC_CTRL2_TEMP_ISRC1_MASK (0xf << 4)
98 #define LRADC_CTRL2_TEMP_ISRC1_OFFSET 4
[all …]
H A Dregs-power-mx28.h1 /* SPDX-License-Identifier: GPL-2.0+ */
11 #include <asm/mach-imx/regs-common.h>
40 uint32_t reserved[4];
66 #define POWER_CTRL_ENIRQ_BATT_BO (1 << 12)
70 #define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8)
74 #define POWER_CTRL_VBUS_VALID_IRQ (1 << 4)
90 #define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12)
91 #define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12
92 #define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8)
93 #define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
23 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(4)
35 #define ICPU_PI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
36 #define ICPU_PI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
44 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
45 #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
50 #define ICPU_SW_MODE_SW_SPI_SCK BIT(12)
54 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
55 #define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
56 #define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5)
[all …]
/openbmc/u-boot/post/lib_powerpc/
H A Dasm.S1 /* SPDX-License-Identifier: GPL-2.0+ */
20 stwu r0, -4(r1)
34 addi r1, r1, 4
43 stwu r0, -4(r1)
59 addi r1, r1, 4
68 stwu r0, -4(r1)
69 stwu r4, -4(r1)
79 lwz r0, 4(r1)
80 addi r1, r1, 8
89 stwu r0, -4(r1)
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
23 #define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(12)
27 #define ICPU_GENERAL_CTRL_IF_PI_SLV_DONEPOL BIT(8)
30 #define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4))
31 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(5, 4)
32 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4)
45 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
46 #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
51 #define ICPU_SW_MODE_SW_SPI_SCK BIT(12)
55 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
[all …]
/openbmc/openbmc/meta-facebook/meta-catalina/recipes-phosphor/sensors/phosphor-virtual-sensor/catalina/
H A Dvirtual_sensor_config.json79 …_PWM_PCT, FAN2_PWM_PCT, FAN3_PWM_PCT, FAN4_PWM_PCT, FAN5_PWM_PCT, FAN6_PWM_PCT, FAN7_PWM_PCT)) - ",
88 "MinValue": -127
167 "var CAL_OFS[11]:={-1.0, -1.0, -1.0, -1.5, -1.5, -2.5, -2.5, -3.0, -3.0, -3.0, -3.0};",
169 …FIOBOARD_REMOTE_INLET_TEMP_C+(CAL_OFS[0]+((DUTY_AVG-DUTY_OFS[0])*(CAL_OFS[1]-CAL_OFS[0])/(DUTY_OFS…
170 …FIOBOARD_REMOTE_INLET_TEMP_C+(CAL_OFS[1]+((DUTY_AVG-DUTY_OFS[1])*(CAL_OFS[2]-CAL_OFS[1])/(DUTY_OFS…
171 …FIOBOARD_REMOTE_INLET_TEMP_C+(CAL_OFS[2]+((DUTY_AVG-DUTY_OFS[2])*(CAL_OFS[3]-CAL_OFS[2])/(DUTY_OFS…
172 …ge(DUTY_OFS[4],DUTY_AVG,DUTY_OFS[3]): FIOBOARD_REMOTE_INLET_TEMP_C+(CAL_OFS[3]+((DUTY_AVG-DUTY_OFS…
173 …DUTY_AVG,DUTY_OFS[4]): FIOBOARD_REMOTE_INLET_TEMP_C+(CAL_OFS[4]+((DUTY_AVG-DUTY_OFS[4])*(CAL_OFS[5…
174 …FIOBOARD_REMOTE_INLET_TEMP_C+(CAL_OFS[5]+((DUTY_AVG-DUTY_OFS[5])*(CAL_OFS[6]-CAL_OFS[5])/(DUTY_OFS…
175 …FIOBOARD_REMOTE_INLET_TEMP_C+(CAL_OFS[6]+((DUTY_AVG-DUTY_OFS[6])*(CAL_OFS[7]-CAL_OFS[6])/(DUTY_OFS…
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
24 #define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(8)
28 #define ICPU_GENERAL_CTRL_IF_PI_SLV_ENA BIT(4)
40 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
41 #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
46 #define ICPU_SW_MODE_SW_SPI_SCK BIT(12)
50 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
51 #define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
52 #define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5)
53 #define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1))
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dimmap_86xx.h19 /* Local-Access Registers and MCM Registers(0x0000-0x2000) */
21 uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
22 char res1[4];
23 uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
24 char res2[4];
25 uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
26 char res3[12];
27 uint bptr; /* 0x20 - Boot Page Translation Register */
29 uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
30 char res5[4];
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
24 #define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(12)
28 #define ICPU_GENERAL_CTRL_IF_PI_SLV_ENA BIT(8)
31 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(7, 6)) >> 4)
32 #define ICPU_GENERAL_CTRL_IF_SI1_OWNER(x) (((x) << 4) & GENMASK(5, 4))
33 #define ICPU_GENERAL_CTRL_IF_SI1_OWNER_M GENMASK(5, 4)
34 #define ICPU_GENERAL_CTRL_IF_SI1_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4)
47 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
48 #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
53 #define ICPU_SW_MODE_SW_SPI_SCK BIT(12)
[all …]

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