Searched +full:5 +full:gbase +full:- +full:kx (Results 1 – 11 of 11) sorted by relevance
/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | microchip,sparx5-serdes.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Steen Hegelund <steen.hegelund@microchip.com> 21 * Rx built-in fault detector (loss-of-lock/loss-of-signal) 22 * Adjustable tx de-emphasis (FFE) 31 The SERDES6G is a high-speed SERDES interface, which can operate at 34 * 100 Mbps (100BASE-FX) 35 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX) [all …]
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/openbmc/u-boot/include/linux/ |
H A D | mdio.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 4 * Copyright 2006-2009 Solarflare Communications Inc. 22 #define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */ 24 #define MDIO_MMD_AN 7 /* Auto-Negotiation */ 35 #define MDIO_DEVS1 5 /* Devices in package */ 52 /* Media-dependent registers. */ 53 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */ 54 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */ 55 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A. 56 * Lanes B-D are numbered 134-136. */ [all …]
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/openbmc/linux/include/uapi/linux/ |
H A D | mdio.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 4 * Copyright 2006-2009 Solarflare Communications Inc. 23 #define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */ 25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */ 36 #define MDIO_DEVS1 5 /* Devices in package */ 49 #define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */ 58 /* Media-dependent registers. */ 59 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */ 60 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */ 61 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A. [all …]
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/openbmc/u-boot/board/freescale/t208xqds/ |
H A D | README | 1 The T2080QDS is a high-performance computing evaluation, development and 5 ------------------ 6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power 7 Architecture processor cores with high-performance datapath acceleration 12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz 13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC) 14 - Hierarchical interconnect fabric 15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving 16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration 17 - 16 SerDes lanes up to 10.3125 GHz [all …]
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H A D | eth_t208xqds.c | 1 // SPDX-License-Identifier: GPL-2.0+ 38 #define EMI1_SLOT5 5 43 #define EMI1_SLOT5 5 134 struct t208xqds_mdio *priv = bus->priv; in t208xqds_mdio_read() 136 t208xqds_mux_mdio(priv->muxval); in t208xqds_mdio_read() 138 return priv->realbus->read(priv->realbus, addr, devad, regnum); in t208xqds_mdio_read() 144 struct t208xqds_mdio *priv = bus->priv; in t208xqds_mdio_write() 146 t208xqds_mux_mdio(priv->muxval); in t208xqds_mdio_write() 148 return priv->realbus->write(priv->realbus, addr, devad, regnum, value); in t208xqds_mdio_write() 153 struct t208xqds_mdio *priv = bus->priv; in t208xqds_mdio_reset() [all …]
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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
H A D | README.soc | 7 5. LS1046A 13 --------- 14 The LS1043A integrated multicore processor combines four ARM Cortex-A53 20 - Four 64-bit ARM Cortex-A53 CPUs 21 - 1 MB unified L2 Cache 22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving 24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the 26 - Packet parsing, classification, and distribution (FMan) 27 - Queue management for scheduling, packet sequencing, and congestion 29 - Hardware buffer management for buffer allocation and de-allocation (BMan) [all …]
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/openbmc/linux/include/linux/ |
H A D | phy.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c 79 * Set phydev->irq to PHY_POLL if interrupts are not supported, 83 #define PHY_POLL -1 84 #define PHY_MAC_INTERRUPT -2 93 * enum phy_interface_t - Interface Mode definitions 95 * @PHY_INTERFACE_MODE_NA: Not Applicable - don't touch 97 * @PHY_INTERFACE_MODE_MII: Media-independent interface 98 * @PHY_INTERFACE_MODE_GMII: Gigabit media-independent interface 99 * @PHY_INTERFACE_MODE_SGMII: Serial gigabit media-independent interface [all …]
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/openbmc/linux/drivers/net/ethernet/amd/xgbe/ |
H A D | xgbe-phy-v2.c | 125 #include "xgbe-common.h" 149 /* Rate-change complete wait/retry count */ 225 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5) 276 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \ 277 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE)) 284 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE " 285 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 " 306 /* Re-driver related definitions */ 320 XGBE_PHY_REDRV_MODE_CX = 5, 375 /* Re-driver support */ [all …]
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/openbmc/linux/drivers/net/ethernet/freescale/fman/ |
H A D | fman_memac.c | 1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later 3 * Copyright 2008 - 2015 Freescale Semiconductor Inc. 14 #include <linux/pcs-lynx.h> 56 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */ 57 #define IF_MODE_10G 0x00000000 /* 30-31 10G interface */ 58 #define IF_MODE_MII 0x00000001 /* 30-31 MII interface */ 59 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */ 62 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */ 63 #define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */ 64 #define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */ [all …]
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/openbmc/linux/drivers/net/ethernet/intel/ixgbe/ |
H A D | ixgbe_82599.c | 1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 65 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_mac_link_ops_82599() 70 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && in ixgbe_init_mac_link_ops_82599() 72 mac->ops.disable_tx_laser = in ixgbe_init_mac_link_ops_82599() 74 mac->ops.enable_tx_laser = in ixgbe_init_mac_link_ops_82599() 76 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; in ixgbe_init_mac_link_ops_82599() 78 mac->ops.disable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599() 79 mac->ops.enable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599() 80 mac->ops.flap_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599() [all …]
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/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/ |
H A D | bnx2x_link.c | 1 /* Copyright 2008-2013 Broadcom Corporation 8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL"). 43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) 161 #define SFP_EEPROM_10G_COMP_CODE_LR_MASK (1<<5) 205 (_phy)->def_md_devad, \ 211 (_phy)->def_md_devad, \ 239 * bnx2x_check_lfa - This function checks if link reinitialization is required, 251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa() 254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa() 257 /* NOTE: must be first condition checked - in bnx2x_check_lfa() [all …]
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