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/openbmc/linux/drivers/media/i2c/cx25840/
H A Dcx25840-audio.c17 * NTSC Color subcarrier freq * 8 = 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
26 * ref_freq = 28.636360 MHz
28 * ref_freq = 28.636363 MHz
46 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
47 * 432 MHz pre-postdivide in cx25840_set_audclk_freq()
52 * 28636363 * 0x6.dd9cf70/0x10 = 32000 * 384 in cx25840_set_audclk_freq()
53 * 196.6 MHz pre-postdivide in cx25840_set_audclk_freq()
54 * FIXME < 200 MHz is out of specified valid range in cx25840_set_audclk_freq()
61 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq()
84 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
[all …]
/openbmc/u-boot/board/sunxi/
H A Ddram_timings_sun4i.h4 # if CONFIG_DRAM_CLK <= 360 /* DDR3-1066F @360MHz, timings: 6-5-5-14 */
10 # elif CONFIG_DRAM_CLK <= 384 /* DDR3-1066F @384MHz, timings: 6-6-6-15 */
16 # elif CONFIG_DRAM_CLK <= 396 /* DDR3-1066F @396MHz, timings: 6-6-6-15 */
22 # elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066F @408MHz, timings: 7-6-6-16 */
28 # elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066F @432MHz, timings: 7-6-6-17 */
34 # elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066F @456MHz, timings: 7-6-6-18 */
40 # elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066F @468MHz, timings: 7-7-7-18 */
46 # elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066F @480MHz, timings: 7-7-7-18 */
52 # elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066F @504MHz, timings: 7-7-7-19 */
58 # elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066F @528MHz, timings: 7-7-7-20 */
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-av-audio.c25 * 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz in set_audclk_freq()
41 * crystal value at all, it will assume 28.636360 MHz, the crystal in set_audclk_freq()
44 * xtal_freq = 28.636360 MHz in set_audclk_freq()
49 * Below I aim to run the PLLs' VCOs near 400 MHz to minimize error. in set_audclk_freq()
66 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
70 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq()
82 /* AUD_COUNT = 0x2fff = 8 samples * 4 * 384 - 1 */ in set_audclk_freq()
101 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
105 /* xtal * 0xe.3150f90/0x18 = 44100 * 384: 406 MHz p-pd*/ in set_audclk_freq()
117 /* AUD_COUNT = 0x92ff = 49 samples * 2 * 384 - 1 */ in set_audclk_freq()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3399.h69 #define MHz 1000000 macro
71 #define OSC_HZ (24*MHz)
72 #define LPLL_HZ (600*MHz)
73 #define BPLL_HZ (600*MHz)
74 #define GPLL_HZ (594*MHz)
75 #define CPLL_HZ (384*MHz)
76 #define PPLL_HZ (676*MHz)
78 #define PMU_PCLK_HZ (48*MHz)
80 #define ACLKM_CORE_L_HZ (300*MHz)
81 #define ATCLK_CORE_L_HZ (300*MHz)
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dcs42xx8.c188 * 0 | 0 | 0 |1.029MHz to 12.8MHz | 256 | 128 | 64 |
189 * 0 | 0 | 1 |1.536MHz to 19.2MHz | 384 | 192 | 96 |
190 * 0 | 1 | 0 |2.048MHz to 25.6MHz | 512 | 256 | 128 |
191 * 0 | 1 | 1 |3.072MHz to 38.4MHz | 768 | 384 | 192 |
192 * 1 | x | x |4.096MHz to 51.2MHz |1024 | 512 | 256 |
196 { 2, 1536000, 19200000, {384, 192, 96} },
198 { 6, 3072000, 38400000, {768, 384, 192} },
/openbmc/u-boot/include/configs/
H A Dsocrates.h36 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
38 * The board, however, can run at 66MHz. In any event, this value
131 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */
160 /* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
204 /* PCI is clocked by the external source at 33 MHz */
H A Dmpc8308_p1m.h34 * if CLKIN is 66.66MHz, then
35 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
36 * We choose the A type silicon as default, so the core is 400Mhz.
195 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
H A DTQM834x.h25 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
31 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
141 /* Reserve 384 kB = 3 sect. for Mon */
142 #define CONFIG_SYS_MONITOR_LEN (384 * 1024)
H A Dhrcon.h30 * if CLKIN is 66.66MHz, then
31 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
32 * We choose the A type silicon as default, so the core is 400Mhz.
182 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
H A Dstrider.h30 * if CLKIN is 66.66MHz, then
31 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
32 * We choose the A type silicon as default, so the core is 400Mhz.
182 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
H A Dsh7785lcr.h26 #define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024)
81 #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
H A Dtricorder.h46 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
84 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */
190 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
H A Dnokia_rx51.h65 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
109 #define PART2_SIZE 384
312 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
H A Dsmdkc100.h26 /* input clock of PLL: SMDKC100 has 12MHz input clock */
113 #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/mvm/
H A Drfi.c11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
15 /* frequency 2667MHz */
20 /* frequency 2933MHz */
27 /* frequency 3200MHz */
32 /* frequency 3733MHz */
37 /* frequency 4000MHz */
42 /* frequency 4267MHz */
47 /* frequency 4400MHz */
52 /* frequency 5200MHz */
57 /* frequency 5600MHz */
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dmacmodes.c36 /* 512x384, 60Hz, Non-Interlaced (15.67 MHz dot clock) */
37 "mac2", 60, 512, 384, 63828, 80, 16, 19, 1, 32, 3,
40 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
44 /* 640x480, 67Hz, Non-Interlaced (30.0 MHz dotclock) */
48 /* 640x870, 75Hz (portrait), Non-Interlaced (57.28 MHz dot clock) */
52 /* 800x600, 56 Hz, Non-Interlaced (36.00 MHz dotclock) */
56 /* 800x600, 60 Hz, Non-Interlaced (40.00 MHz dotclock) */
60 /* 800x600, 72 Hz, Non-Interlaced (50.00 MHz dotclock) */
64 /* 800x600, 75 Hz, Non-Interlaced (49.50 MHz dotclock) */
68 /* 832x624, 75Hz, Non-Interlaced (57.6 MHz dotclock) */
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dtimer.c53 * at a rate of 6.144 MHz. Because the device operates on different clocks
86 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 in realtime_counter_init()
98 * should compensate to avoid the 570ppm (at 20MHz, much worse in realtime_counter_init()
128 num = 384; in realtime_counter_init()
137 /* Program it for 38.4 MHz */ in realtime_counter_init()
/openbmc/u-boot/arch/arm/include/asm/arch-imx8/sci/
H A Dtypes.h21 #define SC_10MHZ 10000000U /* 10MHz */
22 #define SC_20MHZ 20000000U /* 20MHz */
23 #define SC_25MHZ 25000000U /* 25MHz */
24 #define SC_27MHZ 27000000U /* 27MHz */
25 #define SC_40MHZ 40000000U /* 40MHz */
26 #define SC_45MHZ 45000000U /* 45MHz */
27 #define SC_50MHZ 50000000U /* 50MHz */
28 #define SC_60MHZ 60000000U /* 60MHz */
29 #define SC_66MHZ 66666666U /* 66MHz */
30 #define SC_74MHZ 74250000U /* 74.25MHz */
[all …]
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun4i.c113 /* Final catchall entry 384MHz*/
134 axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */ in clock_set_pll1()
135 ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */ in clock_set_pll1()
136 apb0 = 2; /* Max 150MHz */ in clock_set_pll1()
153 /* Switch to 24MHz clock while changing PLL1 */ in clock_set_pll1()
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-data-modul-edm-sbc.dts266 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
401 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
443 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
454 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
804 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
818 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
849 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
866 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_am33xx.c67 { /* 19.2 MHz */
75 { /* 24 MHz */
83 { /* 25 MHz */
91 { /* 26 MHz */
102 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
103 {125, 2, -1, -1, 10, 8, 4}, /* 24 MHz */
104 {40, 0, -1, -1, 10, 8, 4}, /* 25 MHz */
105 {500, 12, -1, -1, 10, 8, 4} /* 26 MHz */
109 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
110 {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
[all …]
/openbmc/u-boot/board/sbc8548/
H A DREADME5 MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz
6 memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
26 a base clock of 66MHz. Note that you need both PCI enabled in U-Boot
29 The second enables PCI support and builds for a 33MHz clock rate. Note
30 that if a 33MHz 32bit card is inserted in the slot, then the whole board
31 will clock down to a 33MHz base clock instead of the default 66MHz. This
33 were previously running at 66MHz. If you want to use a 33MHz PCI card,
35 to flash prior to powering down the board and inserting the 33MHz PCI
40 default 66MHz. Options four and five are just repeats of option two
45 a 33MHz PCI configuration is currently untested.)
[all …]
/openbmc/linux/sound/soc/samsung/
H A Dsmdk_wm8994.c32 /* SMDK has a 16.934MHZ crystal attached to WM8994 */
52 /* AIF1CLK should be >=3MHz for optimal performance */ in smdk_hw_params()
54 pll_out = params_rate(params) * 384; in smdk_hw_params()
/openbmc/linux/Documentation/admin-guide/media/
H A Dsi4713.rst65 Frequency: 1408000 (88.000000 MHz)
70 Frequency range : 76.0 MHz - 108.0 MHz
83 rds_radio_text (str) : min=0 max=384 step=32 value=''
/openbmc/u-boot/arch/arm/cpu/arm920t/ep93xx/
H A Dlowlevel_init.S287 /* 332MHz, giving a 166MHz processor clock. */
292 /* 384MHz, giving a 196MHz processor clock. */
295 /* 400MHz, giving a 200MHz processor clock. */

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