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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Drenesas,cmt.yaml14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
28 - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1
29 - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1
30 - renesas,r8a7740-cmt2 # 32-bit CMT2 on R-Mobile A1
31 - renesas,r8a7740-cmt3 # 32-bit CMT3 on R-Mobile A1
32 - renesas,r8a7740-cmt4 # 32-bit CMT4 on R-Mobile A1
33 - renesas,sh73a0-cmt0 # 32-bit CMT0 on SH-Mobile AG5
34 - renesas,sh73a0-cmt1 # 48-bit CMT1 on SH-Mobile AG5
35 - renesas,sh73a0-cmt2 # 32-bit CMT2 on SH-Mobile AG5
36 - renesas,sh73a0-cmt3 # 32-bit CMT3 on SH-Mobile AG5
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/openbmc/openbmc/poky/meta/classes-recipe/
H A Dsiteinfo.bbclass18 # * bits: Returns the bit size of the target, either "32" or "64"
26 …"allarch": "endian-little bit-32", # bogus, but better than special-casing the checks below for al…
27 "aarch64": "endian-little bit-64 arm-common arm-64",
28 "aarch64_be": "endian-big bit-64 arm-common arm-64",
29 "arc": "endian-little bit-32 arc-common",
30 "arceb": "endian-big bit-32 arc-common",
31 "arm": "endian-little bit-32 arm-common arm-32",
32 "armeb": "endian-big bit-32 arm-common arm-32",
33 "avr32": "endian-big bit-32 avr32-common",
34 "bfin": "endian-little bit-32 bfin-common",
[all …]
/openbmc/linux/Documentation/arch/arm64/
H A Dasymmetric-32bit.rst2 Asymmetric 32-bit SoCs
7 This document describes the impact of asymmetric 32-bit SoCs on the
8 execution of 32-bit (``AArch32``) applications.
16 of the CPUs are capable of executing 32-bit user applications. On such
19 ``execve(2)`` of 32-bit ELF binaries, with the latter returning
21 64-bit-only CPU, then the onlining operation fails and the new CPU is
25 running legacy 32-bit binaries. Unsurprisingly, that doesn't work very
28 It seems inevitable that future SoCs will drop 32-bit support
30 run 32-bit code on one of these transitionary platforms then you would
38 allowing 32-bit tasks to run on an asymmetric 32-bit system requires an
[all …]
/openbmc/linux/drivers/net/fddi/skfp/h/
H A Dskfbi.h40 #define B0_RAP 0x0000 /* 8 bit register address port */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
46 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
47 #define B0_IMSK 0x000c /* 32 bit Interrupt mask register */
52 #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */
53 #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */
54 #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */
[all …]
/openbmc/linux/include/linux/
H A Dmath64.h16 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
17 * @dividend: unsigned 64bit dividend
18 * @divisor: unsigned 32bit divisor
19 * @remainder: pointer to unsigned 32bit remainder
23 * This is commonly provided by 32bit archs to provide an optimized 64bit
33 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
34 * @dividend: signed 64bit dividend
35 * @divisor: signed 32bit divisor
36 * @remainder: pointer to signed 32bit remainder
47 * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder
[all …]
H A Dexportfs.h33 * 32bit inode number, 32 bit generation number.
38 * 32bit inode number, 32 bit generation number,
39 * 32 bit parent directory inode number.
44 * 64 bit object ID, 64 bit root object ID,
45 * 32 bit generation number.
50 * 64 bit object ID, 64 bit root object ID,
51 * 32 bit generation number,
52 * 64 bit parent object ID, 32 bit parent generation.
57 * 64 bit object ID, 64 bit root object ID,
58 * 32 bit generation number,
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/openbmc/linux/drivers/usb/typec/tipd/
H A Dtps6598x.h18 #define TPS_STATUS_PLUG_PRESENT BIT(0)
19 #define TPS_STATUS_PLUG_UPSIDE_DOWN BIT(4)
21 #define TPS_STATUS_PORTROLE BIT(5)
23 #define TPS_STATUS_DATAROLE BIT(6)
25 #define TPS_STATUS_VCONN BIT(7)
27 #define TPS_STATUS_OVERCURRENT BIT(16)
28 #define TPS_STATUS_GOTO_MIN_ACTIVE BIT(26)
29 #define TPS_STATUS_BIST BIT(27)
30 #define TPS_STATUS_HIGH_VOLAGE_WARNING BIT(28)
31 #define TPS_STATUS_HIGH_LOW_VOLTAGE_WARNING BIT(29)
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/openbmc/linux/arch/s390/include/asm/
H A Delf.h13 #define R_390_8 1 /* Direct 8 bit. */
14 #define R_390_12 2 /* Direct 12 bit. */
15 #define R_390_16 3 /* Direct 16 bit. */
16 #define R_390_32 4 /* Direct 32 bit. */
17 #define R_390_PC32 5 /* PC relative 32 bit. */
18 #define R_390_GOT12 6 /* 12 bit GOT offset. */
19 #define R_390_GOT32 7 /* 32 bit GOT offset. */
20 #define R_390_PLT32 8 /* 32 bit PC relative PLT address. */
25 #define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */
26 #define R_390_GOTPC 14 /* 32 bit PC rel. offset to GOT. */
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/openbmc/u-boot/arch/x86/include/asm/arch-broadwell/
H A Drcb.h9 #define ACPIIRQEN 0x31e0 /* 32bit */
11 #define PMSYNC_CONFIG 0x33c4 /* 32bit */
12 #define PMSYNC_CONFIG2 0x33cc /* 32bit */
14 #define DEEP_S3_POL 0x3328 /* 32bit */
17 #define DEEP_S5_POL 0x3330 /* 32bit */
20 #define DEEP_SX_CONFIG 0x3334 /* 32bit */
24 #define PMSYNC_CONFIG 0x33c4 /* 32bit */
25 #define PMSYNC_CONFIG2 0x33cc /* 32bit */
27 #define RC 0x3400 /* 32bit */
28 #define HPTC 0x3404 /* 32bit */
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/openbmc/u-boot/arch/x86/include/asm/arch-ivybridge/
H A Dpch.h136 #define VCH 0x0000 /* 32bit */
137 #define VCAP1 0x0004 /* 32bit */
138 #define VCAP2 0x0008 /* 32bit */
139 #define PVC 0x000c /* 16bit */
140 #define PVS 0x000e /* 16bit */
142 #define V0CAP 0x0010 /* 32bit */
143 #define V0CTL 0x0014 /* 32bit */
144 #define V0STS 0x001a /* 16bit */
146 #define V1CAP 0x001c /* 32bit */
147 #define V1CTL 0x0020 /* 32bit */
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/openbmc/linux/drivers/net/ethernet/marvell/
H A Dskge.h131 /* B0_CTST 16 bit Control/Status register */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
164 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
168 /* Bit 30: reserved */
215 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
238 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
[all …]
H A Dsky2.h41 PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit 9.. 8: GPHY Link Trigger Timer */
48 PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
49 PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
50 PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
52 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
53 PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
57 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
60 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
91 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
94 P_PEX_LTSSM_STAT_MSK = 0x7fL<<25, /* Bit 31..25: PEX LTSSM Mask */
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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dmc13xxx.txt55 sw1a : regulator SW1A (register 24, bit 0)
56 sw1b : regulator SW1B (register 25, bit 0)
57 sw2a : regulator SW2A (register 26, bit 0)
58 sw2b : regulator SW2B (register 27, bit 0)
59 sw3 : regulator SW3 (register 29, bit 20)
60 vaudio : regulator VAUDIO (register 32, bit 0)
61 viohi : regulator VIOHI (register 32, bit 3)
62 violo : regulator VIOLO (register 32, bit 6)
63 vdig : regulator VDIG (register 32, bit 9)
64 vgen : regulator VGEN (register 32, bit 12)
[all …]
/openbmc/openbmc/poky/meta/conf/distro/include/
H A Dtime64.inc13 # Only needed for some 32-bit architectures, some relatively newer
25 # pipewire-v4l2 explicitly sets _FILE_OFFSET_BITS=32 to get access to
26 # both 32 and 64 bit file APIs. But it does not handle the time side?
34 INSANE_SKIP:append:pn-gcc-sanitizers = " 32bit-time"
35 INSANE_SKIP:append:pn-glibc = " 32bit-time"
36 INSANE_SKIP:append:pn-glibc-y2038-tests = " 32bit-time"
38 # Strace has tests that call 32 bit API directly, which is fair enough, e.g.
39 # /usr/lib/strace/ptest/tests/ioctl_termios uses 32-bit api 'ioctl'
40 INSANE_SKIP:append:pn-strace = " 32bit-time"
42 # Pseudo has to wrap all glibc calls including the 32 bit ones even
[all …]
/openbmc/linux/drivers/net/ethernet/cavium/liquidio/
H A Dcn66xx_regs.h89 /* 1 register (32-bit) to enable Input queues */
92 /* 1 register (32-bit) to enable Output queues */
95 /* 1 register (32-bit) to determine whether Output queues are in reset. */
98 /* 1 register (32-bit) to determine whether Input queues are in reset. */
103 /* 1 register (32-bit) - instr. size of each input queue. */
106 /* 32 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
109 /* 32 registers for Input Queue Start Addr - SLI_PKT0_INSTR_BADDR */
112 /* 32 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
115 /* 32 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */
118 /* 32 registers for Instruction Header Options - SLI_PKT0_INSTR_HEADER */
[all …]
/openbmc/qemu/include/hw/nvram/
H A Dxlnx-efuse.h55 * @data: an array of 32-bit words for which the CRC should be computed
56 * @u32_cnt: the array size in number of 32-bit words
57 * @zpads: the number of 32-bit zeros prepended to @data before computation
59 * This function is used to compute the CRC for an array of 32-bit words,
62 * Returns: the computed 32-bit CRC
70 * @bit: the efuse bit-address to read the data
72 * Returns: the bit, 0 or 1, at @bit of object @s
74 bool xlnx_efuse_get_bit(XlnxEFuse *s, unsigned int bit);
79 * @bit: the efuse bit-address to be written a value of 1
83 bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit);
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/openbmc/linux/lib/
H A Diomap_copy.c10 * __iowrite32_copy - copy data to MMIO space, in 32-bit units
11 * @to: destination, in MMIO space (must be 32-bit aligned)
12 * @from: source (must be 32-bit aligned)
13 * @count: number of 32-bit quantities to copy
15 * Copy data from kernel space to MMIO space, in units of 32 bits at a
33 * __ioread32_copy - copy data from MMIO space, in 32-bit units
34 * @to: destination (must be 32-bit aligned)
35 * @from: source, in MMIO space (must be 32-bit aligned)
36 * @count: number of 32-bit quantities to copy
38 * Copy data from MMIO space to kernel space, in units of 32 bits at a
[all …]
/openbmc/linux/drivers/staging/media/ipu3/
H A Dipu3-abi.h15 #define IMGU_DVS_BLOCK_H 32
31 #define IMGU_ABI_AF_MAX_CELLS_PER_SET 32
32 #define IMGU_ABI_AWB_FR_MAX_CELLS_PER_SET 32
46 #define IMGU_PM_CTRL_START BIT(0)
47 #define IMGU_PM_CTRL_CFG_DONE BIT(1)
48 #define IMGU_PM_CTRL_RACE_TO_HALT BIT(2)
49 #define IMGU_PM_CTRL_NACK_ALL BIT(3)
50 #define IMGU_PM_CTRL_CSS_PWRDN BIT(4)
51 #define IMGU_PM_CTRL_RST_AT_EOF BIT(5)
52 #define IMGU_PM_CTRL_FORCE_HALT BIT(6)
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/openbmc/linux/include/uapi/linux/
H A Dswab.h71 __u32 h = val >> 32; in __fswab64()
72 __u32 l = val & ((1ULL << 32) - 1); in __fswab64()
73 return (((__u64)__fswab32(l)) << 32) | ((__u64)(__fswab32(h))); in __fswab64()
98 * __swab16 - return a byteswapped 16-bit value
111 * __swab32 - return a byteswapped 32-bit value
124 * __swab64 - return a byteswapped 64-bit value
140 #else /* __BITS_PER_LONG == 32 */ in __swab()
146 * __swahw32 - return a word-swapped 32-bit value
157 * __swahb32 - return a high and low byte-swapped 32-bit value
168 * __swab16p - return a byteswapped 16-bit value from a pointer
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/openbmc/linux/fs/ext4/
H A Dinode-test.c43 "1901-12-13 Lower bound of 32bit < 0 timestamp, no extra bits"
45 "1969-12-31 Upper bound of 32bit < 0 timestamp, no extra bits"
47 "1970-01-01 Lower bound of 32bit >=0 timestamp, no extra bits"
49 "2038-01-19 Upper bound of 32bit >=0 timestamp, no extra bits"
51 "2038-01-19 Lower bound of 32bit <0 timestamp, lo extra sec bit on"
53 "2106-02-07 Upper bound of 32bit <0 timestamp, lo extra sec bit on"
55 "2106-02-07 Lower bound of 32bit >=0 timestamp, lo extra sec bit on"
57 "2174-02-25 Upper bound of 32bit >=0 timestamp, lo extra sec bit on"
59 "2174-02-25 Lower bound of 32bit <0 timestamp, hi extra sec bit on"
61 "2242-03-16 Upper bound of 32bit <0 timestamp, hi extra sec bit on"
[all …]
/openbmc/linux/Documentation/admin-guide/
H A Dhighuid.rst2 Notes on the change from 16-bit UIDs to 32-bit UIDs
15 What's left to be done for 32-bit UIDs on all Linux architectures:
22 properly with huge UIDs. If it can deal with 64-bit file offsets on all
27 (currently, the old 16-bit UID and GID are still written to disk, and
28 part of the former pad space is used to store separate 32-bit UID and
31 - Need to validate that OS emulation calls the 16-bit UID
32 compatibility syscalls, if the OS being emulated used 16-bit UIDs, or
33 uses the 32-bit UID system calls properly otherwise.
40 (need to support whatever new 32-bit UID system calls are added to
45 At present, 32-bit UIDs _should_ work for:
[all …]
/openbmc/qemu/include/qemu/
H A Dbitops.h24 #define BIT(nr) (1UL << (nr)) macro
43 * be some guest-visible register view of the bit array.
56 * DOC: 'unsigned long' bit array APIs
63 * set_bit - Set a bit in memory
64 * @nr: the bit to set
76 * set_bit_atomic - Set a bit in memory atomically
77 * @nr: the bit to set
89 * clear_bit - Clears a bit in memory
90 * @nr: Bit to clear
102 * clear_bit_atomic - Clears a bit in memory atomically
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/openbmc/u-boot/include/linux/
H A Dmath64.h14 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
16 * This is commonly provided by 32bit archs to provide an optimized 64bit
26 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
35 * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder
44 * div64_u64 - unsigned 64bit divide with 64bit divisor
52 * div64_s64 - signed 64bit divide with 64bit divisor
59 #elif BITS_PER_LONG == 32
91 * div_u64 - unsigned 64bit divide with 32bit divisor
93 * This is the most common 64bit divide and should be used if possible,
94 * as many 32bit archs can optimize this variant better than a full 64bit
[all …]
/openbmc/linux/Documentation/staging/
H A Dcrc32.rst17 subtract, we just xor. Thus, we tend to get a bit sloppy about
21 To produce a 32-bit CRC, the divisor is actually a 33-bit CRC polynomial.
22 Since it's 33 bits long, bit 32 is always going to be set, so usually the
23 CRC is written in hex with the most significant bit omitted. (If you're
30 little-endian; the most significant bit (sometimes used for parity)
34 Just like with ordinary division, you proceed one digit (bit) at a time.
35 Each step of the division you take one more digit (bit) of the dividend
39 and to make the XOR cancel, it's just a copy of bit 32 of the remainder.
42 throw the quotient bit away, but subtract the appropriate multiple of
44 ready to process the next bit.
[all …]
/openbmc/u-boot/lib/
H A Ddiv64.c9 * Generic C version of 64bit/32bit division and modulo, with
10 * 64bit result and 32bit remainder.
12 * The fast case for (n>>32 == 0) is handled inline by do_div().
24 /* Not needed on 64bit architectures */
25 #if BITS_PER_LONG == 32
33 uint32_t high = rem >> 32; in __div64_32()
35 /* Reduce the thing a bit first */ in __div64_32()
39 res = (uint64_t) high << 32; in __div64_32()
40 rem -= (uint64_t) (high*base) << 32; in __div64_32()
84 * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder
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