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/openbmc/linux/drivers/gpu/drm/radeon/
H A Duvd_v1_0.c32 * uvd_v1_0_get_rptr - get read pointer
35 * @ring: radeon_ring pointer
40 struct radeon_ring *ring) in uvd_v1_0_get_rptr() argument
46 * uvd_v1_0_get_wptr - get write pointer
49 * @ring: radeon_ring pointer
54 struct radeon_ring *ring) in uvd_v1_0_get_wptr() argument
60 * uvd_v1_0_set_wptr - set write pointer
63 * @ring: radeon_ring pointer
68 struct radeon_ring *ring) in uvd_v1_0_set_wptr() argument
70 WREG32(UVD_RBC_RB_WPTR, ring->wptr); in uvd_v1_0_set_wptr()
[all …]
H A Duvd_v2_2.c32 * uvd_v2_2_fence_emit - emit an fence & trap command
37 * Write a fence and a trap command to the ring.
42 struct radeon_ring *ring = &rdev->ring[fence->ring]; in uvd_v2_2_fence_emit() local
43 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v2_2_fence_emit()
45 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); in uvd_v2_2_fence_emit()
46 radeon_ring_write(ring, fence->seq); in uvd_v2_2_fence_emit()
47 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v2_2_fence_emit()
48 radeon_ring_write(ring, lower_32_bits(addr)); in uvd_v2_2_fence_emit()
49 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v2_2_fence_emit()
50 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); in uvd_v2_2_fence_emit()
[all …]
H A Dvce_v1_0.c15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
53 * vce_v1_0_get_rptr - get read pointer
56 * @ring: radeon_ring pointer
61 struct radeon_ring *ring) in vce_v1_0_get_rptr() argument
63 if (ring->idx == TN_RING_TYPE_VCE1_INDEX) in vce_v1_0_get_rptr()
70 * vce_v1_0_get_wptr - get write pointer
73 * @ring: radeon_ring pointer
78 struct radeon_ring *ring) in vce_v1_0_get_wptr() argument
80 if (ring->idx == TN_RING_TYPE_VCE1_INDEX) in vce_v1_0_get_wptr()
87 * vce_v1_0_set_wptr - set write pointer
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H A Dr600_dma.c34 * to the 3D engine (ring buffer, IBs, etc.), but the
36 * different form the PM4 format used by the 3D engine.
43 * r600_dma_get_rptr - get the current read pointer
46 * @ring: radeon ring pointer
51 struct radeon_ring *ring) in r600_dma_get_rptr() argument
55 if (rdev->wb.enabled) in r600_dma_get_rptr()
56 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_dma_get_rptr()
64 * r600_dma_get_wptr - get the current write pointer
67 * @ring: radeon ring pointer
72 struct radeon_ring *ring) in r600_dma_get_wptr() argument
[all …]
/openbmc/linux/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_ring2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Applied Micro X-Gene SoC Ethernet Driver
12 static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring) in xgene_enet_ring_init() argument
14 u32 *ring_cfg = ring->state; in xgene_enet_ring_init()
15 u64 addr = ring->dma; in xgene_enet_ring_init()
17 if (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU) { in xgene_enet_ring_init()
18 ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK); in xgene_enet_ring_init()
19 ring_cfg[3] |= SET_BIT(X2_DEQINTEN); in xgene_enet_ring_init()
27 ring_cfg[3] |= SET_VAL(RINGSIZE, ring->cfgsize) in xgene_enet_ring_init()
34 static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring) in xgene_enet_ring_set_type() argument
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H A Dxgene_enet_hw.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Applied Micro X-Gene SoC Ethernet Driver
13 static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring) in xgene_enet_ring_init() argument
15 u32 *ring_cfg = ring->state; in xgene_enet_ring_init()
16 u64 addr = ring->dma; in xgene_enet_ring_init()
17 enum xgene_enet_ring_cfgsize cfgsize = ring->cfgsize; in xgene_enet_ring_init()
21 ring_cfg[3] |= ACCEPTLERR; in xgene_enet_ring_init()
28 ring_cfg[3] |= addr & CREATE_MASK_ULL(RINGADDRH_POS, RINGADDRH_LEN); in xgene_enet_ring_init()
29 ring_cfg[3] |= ((u32)cfgsize << RINGSIZE_POS) & in xgene_enet_ring_init()
33 static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring) in xgene_enet_ring_set_type() argument
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_2.c74 base = adev->reg_offset[GC_HWIP][0][1]; in sdma_v5_2_get_reg_offset()
79 base = adev->reg_offset[GC_HWIP][0][0]; in sdma_v5_2_get_reg_offset()
83 base = adev->reg_offset[GC_HWIP][0][2]; in sdma_v5_2_get_reg_offset()
84 if (instance == 3) in sdma_v5_2_get_reg_offset()
92 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring) in sdma_v5_2_ring_init_cond_exec() argument
96 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v5_2_ring_init_cond_exec()
97 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_2_ring_init_cond_exec()
98 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_2_ring_init_cond_exec()
99 amdgpu_ring_write(ring, 1); in sdma_v5_2_ring_init_cond_exec()
100 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ in sdma_v5_2_ring_init_cond_exec()
[all …]
H A Duvd_v3_1.c38 * uvd_v3_1_ring_get_rptr - get read pointer
40 * @ring: amdgpu_ring pointer
44 static uint64_t uvd_v3_1_ring_get_rptr(struct amdgpu_ring *ring) in uvd_v3_1_ring_get_rptr() argument
46 struct amdgpu_device *adev = ring->adev; in uvd_v3_1_ring_get_rptr()
52 * uvd_v3_1_ring_get_wptr - get write pointer
54 * @ring: amdgpu_ring pointer
58 static uint64_t uvd_v3_1_ring_get_wptr(struct amdgpu_ring *ring) in uvd_v3_1_ring_get_wptr() argument
60 struct amdgpu_device *adev = ring->adev; in uvd_v3_1_ring_get_wptr()
66 * uvd_v3_1_ring_set_wptr - set write pointer
68 * @ring: amdgpu_ring pointer
[all …]
H A Dmes_v10_1.c49 static void mes_v10_1_ring_set_wptr(struct amdgpu_ring *ring) in mes_v10_1_ring_set_wptr() argument
51 struct amdgpu_device *adev = ring->adev; in mes_v10_1_ring_set_wptr()
53 if (ring->use_doorbell) { in mes_v10_1_ring_set_wptr()
54 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, in mes_v10_1_ring_set_wptr()
55 ring->wptr); in mes_v10_1_ring_set_wptr()
56 WDOORBELL64(ring->doorbell_index, ring->wptr); in mes_v10_1_ring_set_wptr()
62 static u64 mes_v10_1_ring_get_rptr(struct amdgpu_ring *ring) in mes_v10_1_ring_get_rptr() argument
64 return *ring->rptr_cpu_addr; in mes_v10_1_ring_get_rptr()
67 static u64 mes_v10_1_ring_get_wptr(struct amdgpu_ring *ring) in mes_v10_1_ring_get_wptr() argument
71 if (ring->use_doorbell) in mes_v10_1_ring_get_wptr()
[all …]
H A Damdgpu_ring.c40 * Most engines on the GPU are fed via ring buffers. Ring
46 * pointers are equal, the ring is idle. When the host
47 * writes commands to the ring buffer, it increments the
53 * amdgpu_ring_max_ibs - Return max IBs that fit in a single submission.
55 * @type: ring type for which to return the limit.
73 * amdgpu_ring_alloc - allocate space on the ring buffer
75 * @ring: amdgpu_ring structure holding ring information
76 * @ndw: number of dwords to allocate in the ring buffer
78 * Allocate @ndw dwords in the ring buffer (all asics).
81 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw) in amdgpu_ring_alloc() argument
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H A Duvd_v4_2.c52 * uvd_v4_2_ring_get_rptr - get read pointer
54 * @ring: amdgpu_ring pointer
58 static uint64_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) in uvd_v4_2_ring_get_rptr() argument
60 struct amdgpu_device *adev = ring->adev; in uvd_v4_2_ring_get_rptr()
66 * uvd_v4_2_ring_get_wptr - get write pointer
68 * @ring: amdgpu_ring pointer
72 static uint64_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) in uvd_v4_2_ring_get_wptr() argument
74 struct amdgpu_device *adev = ring->adev; in uvd_v4_2_ring_get_wptr()
80 * uvd_v4_2_ring_set_wptr - set write pointer
82 * @ring: amdgpu_ring pointer
[all …]
H A Damdgpu_ih.c24 #include <linux/dma-mapping.h>
30 * amdgpu_ih_ring_init - initialize the IH state
33 * @ih: ih ring to initialize
34 * @ring_size: ring size to allocate
38 * for the IH ring buffer.
47 /* Align ring size */ in amdgpu_ih_ring_init()
50 ih->ring_size = ring_size; in amdgpu_ih_ring_init()
51 ih->ptr_mask = ih->ring_size - 1; in amdgpu_ih_ring_init()
52 ih->rptr = 0; in amdgpu_ih_ring_init()
53 ih->use_bus_addr = use_bus_addr; in amdgpu_ih_ring_init()
[all …]
H A Duvd_v5_0.c50 * uvd_v5_0_ring_get_rptr - get read pointer
52 * @ring: amdgpu_ring pointer
56 static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) in uvd_v5_0_ring_get_rptr() argument
58 struct amdgpu_device *adev = ring->adev; in uvd_v5_0_ring_get_rptr()
64 * uvd_v5_0_ring_get_wptr - get write pointer
66 * @ring: amdgpu_ring pointer
70 static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) in uvd_v5_0_ring_get_wptr() argument
72 struct amdgpu_device *adev = ring->adev; in uvd_v5_0_ring_get_wptr()
78 * uvd_v5_0_ring_set_wptr - set write pointer
80 * @ring: amdgpu_ring pointer
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H A Dvce_v3_0.c15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
59 #define FW_52_8_3 ((52 << 24) | (8 << 16) | (3 << 8))
71 * vce_v3_0_ring_get_rptr - get read pointer
73 * @ring: amdgpu_ring pointer
77 static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring) in vce_v3_0_ring_get_rptr() argument
79 struct amdgpu_device *adev = ring->adev; in vce_v3_0_ring_get_rptr()
82 mutex_lock(&adev->grbm_idx_mutex); in vce_v3_0_ring_get_rptr()
83 if (adev->vce.harvest_config == 0 || in vce_v3_0_ring_get_rptr()
84 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1) in vce_v3_0_ring_get_rptr()
86 else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) in vce_v3_0_ring_get_rptr()
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-sec5.3-0.dtsi36 compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <4>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v5.3-job-ring",
46 "fsl,sec-v5.0-job-ring",
47 "fsl,sec-v4.0-job-ring";
53 compatible = "fsl,sec-v5.3-job-ring",
54 "fsl,sec-v5.0-job-ring",
55 "fsl,sec-v4.0-job-ring";
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/openbmc/u-boot/drivers/usb/host/
H A Dxhci-ring.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on xHCI host controller driver in linux-kernel
25 * Is this TRB a link TRB or was the last TRB the last TRB in this event ring
30 * @param ring pointer to the ring
32 * @param trb poniter to the ring trb
35 static int last_trb(struct xhci_ctrl *ctrl, struct xhci_ring *ring, in last_trb() argument
38 if (ring == ctrl->event_ring) in last_trb()
39 return trb == &seg->trbs[TRBS_PER_SEGMENT]; in last_trb()
41 return TRB_TYPE_LINK_LE32(trb->link.control); in last_trb()
45 * Does this link TRB point to the first segment in a ring,
[all …]
/openbmc/linux/drivers/net/ethernet/freescale/enetc/
H A Denetc_cbdr.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* Copyright 2017-2019 NXP */
11 cbdr->bd_base = dma_alloc_coherent(dev, size, &cbdr->bd_dma_base, in enetc_setup_cbdr()
13 if (!cbdr->bd_base) in enetc_setup_cbdr()
14 return -ENOMEM; in enetc_setup_cbdr()
17 if (!IS_ALIGNED(cbdr->bd_dma_base, 128)) { in enetc_setup_cbdr()
18 dma_free_coherent(dev, size, cbdr->bd_base, in enetc_setup_cbdr()
19 cbdr->bd_dma_base); in enetc_setup_cbdr()
20 return -EINVAL; in enetc_setup_cbdr()
23 cbdr->next_to_clean = 0; in enetc_setup_cbdr()
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/openbmc/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-io.json12 …y the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged …
27 …y the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged …
123 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
129 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
140 …serts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged …
151 …serts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged …
162 …serts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged …
167 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
173 …t 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugge…
184 …serts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged …
[all …]
/openbmc/qemu/hw/net/fsl_etsec/
H A Dregisters.c4 * Copyright (c) 2011-2013 AdaCore
41 {0x05C, "FIFO_RX_ALARM_SHUTOFF", "FIFO receive alarm shut-off threshold register", ACC_RW, 0x00000…
44 {0x09C, "FIFO_TX_STARVE_SHUTOFF", "FIFO transmit starve shut-off register", ACC_RW, 0x00000…
53 {0x140, "TR03WT", "TxBD Rings 0-3 round-robin weightings", ACC_RW, 0x00000000},
54 {0x144, "TR47WT", "TxBD Rings 4-7 round-robin weightings", ACC_RW, 0x00000000},
56 {0x184, "TBPTR0", "TxBD pointer for ring 0", ACC_RW, 0x00000000},
57 {0x18C, "TBPTR1", "TxBD pointer for ring 1", ACC_RW, 0x00000000},
58 {0x194, "TBPTR2", "TxBD pointer for ring 2", ACC_RW, 0x00000000},
59 {0x19C, "TBPTR3", "TxBD pointer for ring 3", ACC_RW, 0x00000000},
60 {0x1A4, "TBPTR4", "TxBD pointer for ring 4", ACC_RW, 0x00000000},
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A Duncore-io.json94 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
100 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
111 …serts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged …
122 …serts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged …
133 …serts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged …
138 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
144 …t 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugge…
155 …serts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged …
166 …serts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged …
177 …serts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged …
[all …]
/openbmc/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_txrx.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
33 * the value of the rate limit is non-zero
40 * i40e_intrl_usec_to_reg - convert interrupt rate limit to register
65 I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */
96 (((pf)->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE) ? \
110 * i.e. RXBUFFER_256 --> 960 byte skb (size-1024 slab)
111 * i.e. RXBUFFER_512 --> 1216 byte skb (size-2048 slab)
139 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len; in i40e_compute_pad()
149 * optimize padding for a 3K buffer instead of a 1.5K buffer. in i40e_skb_pad()
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Dmite.c1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
7 * Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
11 * The PCI-MIO E series driver was originally written by
18 * DAQ-STC reference manual
27 * 321791a.pdf discontinuation of at-mio-16e-10 rev. c
28 * 321808a.pdf about at-mio-16e-10 rev P
29 * 321837a.pdf discontinuation of at-mio-16de-10 rev d
30 * 321838a.pdf about at-mio-16de-10 rev N
73 #define CHOR_ABORT BIT(3) /* stop without emptying fifo */
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/openbmc/linux/drivers/net/can/spi/mcp251xfd/
H A Dmcp251xfd.h1 /* SPDX-License-Identifier: GPL-2.0
3 * mcp251xfd - Microchip MCP251xFD Family CAN controller driver
6 * Marc Kleine-Budde <kernel@pengutronix.de>
16 #include <linux/can/rx-offload.h>
36 #define MCP251XFD_REG_CON_MODE_LISTENONLY 3
69 #define MCP251XFD_REG_DBTCFG_SJW_MASK GENMASK(3, 0)
120 #define MCP251XFD_REG_INT_MODIF BIT(3)
182 #define MCP251XFD_REG_TEFCON_TEFOVIE BIT(3)
188 #define MCP251XFD_REG_TEFSTA_TEFOVIF BIT(3)
200 #define MCP251XFD_REG_TXQCON_PLSIZE_20 3
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/openbmc/linux/drivers/hv/
H A Dring_buffer.c1 // SPDX-License-Identifier: GPL-2.0-only
28 * When we write to the ring buffer, check if the host needs to
32 * ring buffer, it will set the interrupt_mask to
37 * the ring buffer before exiting the read loop. Further,
38 * once the ring buffer is empty, it will clear the
39 * interrupt_mask and re-check to see if new data has
45 * the interrupt. The host expects interrupts only when the ring
46 * transitions from empty to non-empty (or full to non full on the guest
47 * to host ring).
48 * So, base the signaling decision solely on the ring state until the
[all …]
/openbmc/linux/drivers/net/ethernet/intel/iavf/
H A Diavf_txrx.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
32 * the value of the rate limit is non-zero
53 IAVF_ITR_NONE = 3 /* ITR_NONE must not be used as an index */
94 * i.e. RXBUFFER_256 --> 960 byte skb (size-1024 slab)
95 * i.e. RXBUFFER_512 --> 1216 byte skb (size-2048 slab)
123 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len; in iavf_compute_pad()
133 * optimize padding for a 3K buffer instead of a 1.5K buffer. in iavf_skb_pad()
135 * For a 3K buffer we need to add enough padding to allow for in iavf_skb_pad()
137 * cache-line alignment. in iavf_skb_pad()
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