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/openbmc/linux/Documentation/driver-api/
H A Dmtdnand.rst10 The generic NAND driver supports almost all NAND and AG-AND based chips
31 --------------------------
37 - [MTD Interface]
43 - [NAND Interface]
48 - [GENERIC]
53 - [DEFAULT]
65 -------------------------------
71 - [INTERN]
77 - [REPLACEABLE]
86 - [BOARDSPECIFIC]
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/openbmc/linux/drivers/leds/
H A Dleds-ipaq-micro.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/mfd/ipaq-micro.h>
24 struct ipaq_micro *micro = dev_get_drvdata(led_cdev->dev->parent->parent); in micro_leds_brightness_set()
27 * Byte 0 = LED color: 0 = yellow, 1 = green in micro_leds_brightness_set()
29 * Byte 1 = duration (flags?) appears to be ignored in micro_leds_brightness_set()
30 * Byte 2 = green ontime in 1/10 sec (deciseconds) in micro_leds_brightness_set()
32 * 0 = 256/10 second in micro_leds_brightness_set()
33 * Byte 3 = green offtime in 1/10 sec (deciseconds) in micro_leds_brightness_set()
35 * 0 = 256/10 seconds in micro_leds_brightness_set()
45 msg.tx_data[2] = 0; /* Duty cycle 256 */ in micro_leds_brightness_set()
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/openbmc/linux/lib/zstd/compress/
H A Dhist.c7 * - FSE source repository : https://github.com/Cyan4973/FiniteStateEntropy
8 * - Public forum : https://groups.google.com/forum/#!forum/lz4c
10 * This source code is licensed under both the BSD-style license (found in the
13 * You may select, at your option, one of the above-listed licenses.
16 /* --- dependencies --- */
17 #include "../common/mem.h" /* U32, BYTE, etc. */
23 /* --- Error management --- */
26 /*-**************************************************************
32 const BYTE* ip = (const BYTE*)src; in HIST_count_simple()
33 const BYTE* const end = ip + srcSize; in HIST_count_simple()
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H A Dzstd_compress_sequences.c5 * This source code is licensed under both the BSD-style license (found in the
8 * You may select, at your option, one of the above-listed licenses.
11 /*-*************************************
17 * -log2(x / 256) lookup table for x in [0, 256).
19 * Else: Return floor(-log2(x / 256) * 256)
21 static unsigned const kInverseProbabilityLog256[256] = {
32 279, 276, 273, 270, 267, 264, 261, 258, 256, 253, 250, 247,
54 * Returns true if we should use ncount=-1 else we should
73 BYTE wksp[FSE_NCOUNTBOUND]; in ZSTD_NCountCost()
91 unsigned norm = (unsigned)((256 * count[s]) / total); in ZSTD_entropyCost()
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/openbmc/qemu/qapi/
H A Dcrypto.json1 # -*- Mode: Python -*-
30 # @raw: raw bytes. When encoded in JSON only valid UTF-8 sequences
47 # @sha1: SHA-1. Should not be used in any new code, legacy compat only
49 # @sha224: SHA-224. (since 2.7)
51 # @sha256: SHA-256. Current recommended strong hash.
53 # @sha384: SHA-384. (since 2.7)
55 # @sha512: SHA-512. (since 2.7)
57 # @ripemd160: RIPEMD-160. (since 2.7)
70 # @aes-128: AES with 128 bit / 16 byte keys
72 # @aes-192: AES with 192 bit / 24 byte keys
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/openbmc/u-boot/arch/arm/mach-uniphier/boot-device/
H A Dboot-device-pxs2.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2017 Socionext Inc.
12 #include "boot-device.h"
18 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
19 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
25 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
26 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
40 {BOOT_DEVICE_SPI, "SPI (3Byte CS0)"},
41 {BOOT_DEVICE_SPI, "SPI (4Byte CS0)"},
42 {BOOT_DEVICE_SPI, "SPI (3Byte CS1)"},
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/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dfsmc-nand.txt5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
6 - reg : Address range of the mtd chip
7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
10 - bank-width : Width (in bytes) of the device. If not present, the width
11 defaults to 1 byte
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
18 byte 1 TAR : ALE to RE delay, 4 bits are valid. Same format as TCLR.
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
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/openbmc/linux/drivers/mtd/spi-nor/
H A Dspansion.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/mtd/spi-nor.h>
67 * struct spansion_nor_params - Spansion private parameters.
76 * spansion_nor_clear_sr() - Clear the Status Register.
81 const struct spansion_nor_params *priv_params = nor->params->priv; in spansion_nor_clear_sr()
84 if (nor->spimem) { in spansion_nor_clear_sr()
85 struct spi_mem_op op = SPANSION_OP(priv_params->clsr); in spansion_nor_clear_sr()
87 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in spansion_nor_clear_sr()
89 ret = spi_mem_exec_op(nor->spimem, &op); in spansion_nor_clear_sr()
96 dev_dbg(nor->dev, "error %d clearing SR\n", ret); in spansion_nor_clear_sr()
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H A Dwinbond.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/mtd/spi-nor.h>
27 * Unfortunately, Winbond has re-used the same JEDEC ID for both in w25q256_post_bfpt_fixups()
33 if (bfpt_header->major == SFDP_JESD216_MAJOR && in w25q256_post_bfpt_fixups()
34 bfpt_header->minor == SFDP_JESD216A_MINOR) in w25q256_post_bfpt_fixups()
35 nor->flags |= SNOR_F_4B_OPCODES; in w25q256_post_bfpt_fixups()
45 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
64 { "w25q16jv-im/jm", INFO(0xef7015, 0, 64 * 1024, 32)
79 OTP_INFO(256, 3, 0x1000, 0x1000) },
87 OTP_INFO(256, 3, 0x1000, 0x1000) },
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/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Dibm-power10-dual.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #address-cells = <2>;
8 #size-cells = <0>;
10 cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
14 #address-cells = <1>;
15 #size-cells = <1>;
16 chip-id = <0>;
24 compatible = "ibm,fsi-i2c-master";
26 #address-cells = <1>;
27 #size-cells = <0>;
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/openbmc/linux/drivers/gpu/drm/radeon/
H A Dradeon_acpi.h33 * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
34 * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes
47 * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
48 * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes
61 * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
62 * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes
71 * WORD - structure size in bytes (includes size field)
72 * WORD - version
73 * DWORD - supported notifications mask
74 * DWORD - supported functions bit vector
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/openbmc/qemu/target/i386/tcg/
H A Ddecode-new.h27 X86_TYPE_C, /* REG in the modrm byte selects a control register */
28 X86_TYPE_D, /* REG in the modrm byte selects a debug register */
31 X86_TYPE_G, /* REG in the modrm byte selects a GPR */
35 X86_TYPE_L, /* The upper 4 bits of the immediate select a 128-bit register */
36 X86_TYPE_M, /* modrm byte selects a memory operand */
37 X86_TYPE_N, /* R/M in the modrm byte selects an MMX register */
39 X86_TYPE_P, /* reg in the modrm byte selects an MMX register */
41 X86_TYPE_R, /* R/M in the modrm byte selects a register */
43 X86_TYPE_U, /* R/M in the modrm byte selects an XMM/YMM register */
44 X86_TYPE_V, /* reg in the modrm byte selects an XMM/YMM register */
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/openbmc/linux/drivers/gpu/drm/amd/include/
H A Damd_acpi.h48 u8 thermal_state; /* thermal state: state id (0: exit state, non-0: state) */
52 u8 backlight_level; /* panel backlight level (0-255) */
64 u8 ipnut_signal; /* input signal in range 0-255 */
73 u8 min_input_signal; /* max input signal in range 0-255 */
74 u8 max_input_signal; /* min input signal in range 0-255 */
94 u16 client_id; /* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */
108 u16 dgpu_id; /* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */
116 * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
117 * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes
130 * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
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/openbmc/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-fh.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2018-2021, 2023 Intel Corporation
4 * Copyright (C) 2015-2017 Intel Deutschland GmbH
12 #include "iwl-trans.h"
28 * Keep-Warm (KW) buffer base address.
31 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
33 * from going into a power-savings mode that would cause higher DRAM latency,
34 * and possible data over/under-runs, before all Tx/Rx is complete.
38 * automatically invokes keep-warm accesses when normal accesses might not
42 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
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/openbmc/u-boot/include/linux/mtd/
H A Dnand_ecc.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2000-2010 Steven J. Hill <sjhill@realitydiluted.com>
18 * Calculate 3 byte ECC code for 256 byte block
23 * Detect and correct a 1 bit error for 256 byte block
/openbmc/u-boot/fs/yaffs2/
H A Dyaffs_ecc.c2 * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
4 * Copyright (C) 2002-2011 Aleph One Ltd.
19 * The ECC can correct single bit errors in a 256-byte page of data. Thus, two
20 * such ECC blocks are used on a 512-byte NAND page.
28 /* Table generated by gen-ecc.c
30 * for each byte of data. These are instead provided in a table in bits7..2.
71 /* Calculate the ECC for a 256-byte block of data */
81 for (i = 0; i < 256; i++) { in yaffs_ecc_calc()
85 if (b & 0x01) { /* odd number of bits in the byte */ in yaffs_ecc_calc()
133 /* Correct the ECC on a 256 byte block of data */
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/openbmc/linux/drivers/net/ethernet/pasemi/
H A Dpasemi_mac_ethtool.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2006-2008 PA Semi, Inc
19 { "rx-drops" },
20 { "rx-bytes" },
21 { "rx-packets" },
22 { "rx-broadcast-packets" },
23 { "rx-multicast-packets" },
24 { "rx-crc-errors" },
25 { "rx-undersize-errors" },
26 { "rx-oversize-errors" },
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/openbmc/linux/lib/crypto/
H A Dgf128mul.c1 /* gf128mul.c - GF(2^128) multiplication functions
17 ---------------------------------------------------------------------------
44 ---------------------------------------------------------------------------
92 * Given a value i in 0..255 as the byte overflow when a field element
94 * 16-bit value that must be XOR-ed into the low-degree end of the
98 * the "be" convention where the highest-order bit is the coefficient of
99 * the highest-degree polynomial term, and one for the "le" convention
100 * where the highest-order bit is the coefficient of the lowest-degree
101 * polynomial term. In both cases the values are stored in CPU byte
107 * Therefore, provided that the appropriate byte endianness conversions
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/openbmc/linux/arch/sparc/lib/
H A DM7memset.S15 * Fast assembler language version of the following C-program for memset
16 * which represents the `standard' for the C-library.
25 * } while (--n != 0);
34 * For less than 32 bytes stores, align the address on 4 byte boundary.
35 * Then store as many 4-byte chunks, followed by trailing bytes.
37 * For sizes greater than 32 bytes, align the address on 8 byte boundary.
39 * store 8-bytes chunks to align the address on 64 byte boundary
42 * 64-byte cache line to zero which will also clear the
49 * In the main loop, continue pre-setting the first long
56 * store remaining data in 64-byte chunks until less than
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/openbmc/linux/drivers/scsi/qedi/
H A Dqedi_nvm_iscsi_cfg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #define NUM_OF_ISCSI_PF_SUPPORTED 4 /* One PF per Port -
17 #define NVM_ISCSI_CFG_DHCP_NAME_MAX_LEN 256
21 u8 byte[NVM_ISCSI_CFG_DHCP_NAME_MAX_LEN]; member
27 u8 byte[NVM_ISCSI_IPV4_ADDR_BYTE_LEN]; member
33 u8 byte[NVM_ISCSI_IPV6_ADDR_BYTE_LEN]; member
74 #define NVM_ISCSI_CFG_ISCSI_NAME_MAX_LEN 256
77 u8 byte[NVM_ISCSI_CFG_ISCSI_NAME_MAX_LEN]; member
80 #define NVM_ISCSI_CFG_CHAP_NAME_MAX_LEN 256
83 u8 byte[NVM_ISCSI_CFG_CHAP_NAME_MAX_LEN]; member
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/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dnand_ecc.c1 // SPDX-License-Identifier: GPL-2.0+
4 * corrects 1 bit errors in a 256 byte block of data.
8 * Copyright (C) 2000-2004 Steven J. Hill (sjhill@realitydiluted.com)
32 * NAND-SPL has no sofware ECC for now, so don't include nand_calculate_ecc(),
38 * Pre-calculated 256-way 1 byte column parity
60 * nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256-byte block
75 for(i = 0; i < 256; i++) { in nand_calculate_ecc()
76 /* Get CP0 - CP5 from table */ in nand_calculate_ecc()
87 /* Create non-inverted ECC code from line parity */ in nand_calculate_ecc()
88 tmp1 = (reg3 & 0x80) >> 0; /* B7 -> B7 */ in nand_calculate_ecc()
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/openbmc/linux/arch/powerpc/crypto/
H A Dghashp10-ppc.pl2 # SPDX-License-Identifier: GPL-2.0
26 # version is ~2.1x slower than hardware-assisted AES-128-CTR, ~12x
27 # faster than "4-bit" integer-only compiler-generated 64-bit code.
48 ( $xlate="${dir}ppc-xlate.pl" and -f $xlate ) or
49 ( $xlate="${dir}../../perlasm/ppc-xlate.pl" and -f $xlate) or
50 die "can't locate ppc-xlate.pl";
70 mfspr $vrsave,256
72 mtspr 256,r0
79 le?vxor 5,5,6 # set a b-endian mask
82 vspltisb $xC2,-16 # 0xf0
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/openbmc/u-boot/lib/libavb/
H A Davb_crypto.h1 /* SPDX-License-Identifier: MIT */
19 /* Size of a RSA-2048 signature. */
20 #define AVB_RSA2048_NUM_BYTES 256
22 /* Size of a RSA-4096 signature. */
25 /* Size of a RSA-8192 signature. */
28 /* Size in bytes of a SHA-1 digest. */
31 /* Size in bytes of a SHA-256 digest. */
34 /* Size in bytes of a SHA-512 digest. */
62 * SHA-256, resulting in 32 bytes of hash digest data. This hash is
63 * signed with a 2048-bit RSA key. The field |hash_size| must be 32,
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/openbmc/linux/drivers/crypto/vmx/
H A Dghashp8-ppc.pl2 # SPDX-License-Identifier: GPL-2.0
26 # version is ~2.1x slower than hardware-assisted AES-128-CTR, ~12x
27 # faster than "4-bit" integer-only compiler-generated 64-bit code.
48 ( $xlate="${dir}ppc-xlate.pl" and -f $xlate ) or
49 ( $xlate="${dir}../../perlasm/ppc-xlate.pl" and -f $xlate) or
50 die "can't locate ppc-xlate.pl";
68 mfspr $vrsave,256
70 mtspr 256,r0
77 le?vxor 5,5,6 # set a b-endian mask
80 vspltisb $xC2,-16 # 0xf0
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/openbmc/linux/Documentation/virt/kvm/devices/
H A Dmpic.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0
10 - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2
20 KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
21 Base address of the 256 KiB MPIC register space. Must be
25 KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
27 "attr" is the byte offset into the MPIC register space. Accesses
28 must be 4-byte aligned.
33 KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
37 For edge-triggered interrupts: Writing 1 is considered an activating
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