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/openbmc/openbmc-test-automation/data/
H A Dipmi_raw_cmd_table.py6 - Define IPMI interface index, commands and expected output.
14 # openbmc/meta-openbmc-machines/meta-openpower/meta-ibm/meta-witherspoon/recipe
15 # s-phosphor/ipmi/phosphor-ipmi-host/cipher_list.json
17 unsupported_ciphers = ["1", "2", "15", "16"]
126 "Get GUID bytes 1 through 16.",
153 "1st byte is instance capacity, last two bytes is activation"
162 "Last two bits are payload vlan number, - FFFFh if VLAN"
245 "0x04 0x20 1"
266 "don't log bit enabled",
268 "don't log bit disabled",
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/openbmc/linux/Documentation/virt/hyperv/
H A Doverview.rst1 .. SPDX-License-Identifier: GPL-2.0
6 enlightened guest on Microsoft's Hyper-V hypervisor. Hyper-V
7 consists primarily of a bare-metal hypervisor plus a virtual machine
10 partitions. In this documentation, references to Hyper-V usually
15 Hyper-V runs on x86/x64 and arm64 architectures, and Linux guests
16 are supported on both. The functionality and behavior of Hyper-V is
19 Linux Guest Communication with Hyper-V
20 --------------------------------------
21 Linux guests communicate with Hyper-V in four different ways:
23 * Implicit traps: As defined by the x86/x64 or arm64 architecture,
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/openbmc/libcper/include/libcper/
H A DCper.h4 Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
17 #include <libcper/common-utils.h>
23 #pragma pack(push, 1)
40 /// The validation bit mask indicates the validity of the following fields
49 /// Timestamp is precise if this bit is set and correlates to the time of the
55 /// Hexadecimal string representation of a 64bit integer
56 /// 16 digits + 2 char + 1 null termination
113 { 0xA6, 0x98, 0xF3, 0x62, 0xD4, 0x64, 0xB3, 0x8F } }
249 { 0x8f, 0x1b, 0xaa, 0x62, 0xde, 0x3e, 0x2c, 0x64 } }
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/openbmc/linux/drivers/staging/media/meson/vdec/
H A Dcodec_h264.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <media/v4l2-mem2mem.h>
8 #include <media/videobuf2-dma-contig.h>
26 #define CMD_SRC_CHANGE 1
32 #define SEI_DATA_READY BIT(15)
45 #define ERROR_FLAG BIT(9)
57 #define AR_PRESENT_FLAG BIT(0)
62 * This is a 16x16 encoded picture that will trigger drain firmware-side.
72 0x63, 0x6f, 0x64, 0x65, 0x63, 0x20, 0x2d, 0x20, 0x43, 0x6f, 0x70, 0x79,
75 0x77, 0x77, 0x77, 0x2e, 0x76, 0x69, 0x64, 0x65, 0x6f, 0x6c, 0x61, 0x6e,
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/openbmc/openbmc-test-automation/ipmi/
H A Dtest_ipmi_watchdog.robot21 Test IPMI Watchdog Timer Does Not Log Bit
22 [Documentation] Execute out of band set/get do not log bit for watchdog timer.
28 ... ${IPMI_RAW_CMD['Watchdog']['Get'][1]}
32 Test IPMI Watchdog Timer Stop Bit
33 [Documentation] Execute out of band set/get stop/resume timer stop bit for watchdog timer.
60 Test IPMI Watchdog Timer Pre-Timeout Interrupt Bits
61 [Documentation] Execute out of band set/get pre-timeout interrupt bits for watchdog timer.
62 [Tags] Test_IPMI_Watchdog_Timer_Pre-Timeout_Interrupt_Bits
133 # Example: Get watchdog response is 0x06 0x24 0x05 0x00 0x64 0x00 0x64 0x00.
134 # Start_timer_value is bits 6 - 7; set to 0x64 0x00 (100 ms decimal).
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/openbmc/linux/include/linux/
H A Dcper.h1 /* SPDX-License-Identifier: GPL-2.0-only */
80 /* Non-Maskable Interrupt */
87 0xD4, 0x64, 0xB3, 0x8F)
130 /* If set, the component must be re-initialized or re-enabled prior to use */
181 /* PCI/PCI-X Bus */
191 0xDE, 0x3E, 0x2C, 0x64)
257 #define CPER_ARM_VALID_MPIDR BIT(0)
258 #define CPER_ARM_VALID_AFFINITY_LEVEL BIT(1)
259 #define CPER_ARM_VALID_RUNNING_STATE BIT(2)
260 #define CPER_ARM_VALID_VENDOR_INFO BIT(3)
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/openbmc/linux/drivers/media/platform/qcom/venus/
H A Dhfi_venus_io.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
14 #define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)
15 #define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)
30 #define VIDC_CTRL_INIT_RESERVED_BITS31_1_SHIFT 1
42 #define CPU_CS_SCIACMDARG0_PC_READY BIT(8)
43 #define CPU_CS_SCIACMDARG0_INIT_IDLE_MSG_MASK BIT(30)
56 #define UC_REGION_ADDR 0x64
117 #define WRAPPER_VDEC_VENC_AHB_BRIDGE_SYNC_RESET 0x64
121 #define WRAPPER_CPU_AXI_HALT_HALT BIT(16)
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/openbmc/u-boot/include/
H A Di8042.h1 /* SPDX-License-Identifier: GPL-2.0+ */
7 /* i8042.h - Intel 8042 keyboard driver header */
15 #define I8042_STS_REG 0x64 /* keyboard status read */
16 #define I8042_CMD_REG 0x64 /* keyboard ctrl write */
18 /* Status register bit defines */
19 #define STATUS_OBF (1 << 0)
20 #define STATUS_IBF (1 << 1)
22 /* Configuration byte bit defines */
23 #define CONFIG_KIRQ_EN (1 << 0)
24 #define CONFIG_MIRQ_EN (1 << 1)
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/openbmc/linux/include/video/
H A Dtdfx.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <linux/i2c-algo-bit.h>
34 #define HWCURLOC 0x64
76 #define COLORFORE (0x00100000 + 0x64)
91 #define AUTOINC_DSTX BIT(10)
92 #define AUTOINC_DSTY BIT(11)
98 #define STATUS_RETRACE BIT(6)
99 #define STATUS_BUSY BIT(9)
100 #define MISCINIT1_CLUT_INV BIT(0)
101 #define MISCINIT1_2DBLOCK_DIS BIT(15)
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/openbmc/linux/drivers/gpu/drm/rockchip/
H A Drockchip_drm_vop2.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author:Mark Yao <mark.yao@rock-chips.com>
15 #define VOP_FEATURE_OUTPUT_10BIT BIT(0)
17 #define WIN_FEATURE_AFBDC BIT(0)
18 #define WIN_FEATURE_CLUSTER BIT(1)
155 #define FS_NEW_INTR BIT(4)
156 #define ADDR_SAME_INTR BIT(5)
157 #define LINE_FLAG1_INTR BIT(6)
158 #define WIN0_EMPTY_INTR BIT(7)
159 #define WIN1_EMPTY_INTR BIT(8)
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/openbmc/u-boot/arch/mips/mach-mt7620/
H A Dddr_calibrate.c1 // SPDX-License-Identifier: GPL-2.0+
8 * https://github.com/MediaTek-Labs/linkit-smart-uboot.git
13 * Most functions in this file are copied from the MediaTek U-Boot
15 * implement this differently. So its mostly a cleaned-up version of
31 #define CPU_FRAC_DIV 1
69 "pref %0, %1\n" \
91 nc_addr < (0xa0000000 + DRAM_BUTTOM - NUM_OF_CACHELINE * 32); in test_loop()
93 writel(0x00007474, (void *)MT76XX_MEMCTRL_BASE + 0x64); in test_loop()
102 (((k == 1) ? coarse_dqs[dqs] : test_dqs) << 12) | in test_loop()
104 (void *)MT76XX_MEMCTRL_BASE + 0x64); in test_loop()
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/openbmc/linux/drivers/bus/mhi/
H A Dcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
27 #define ECABAP_HIGHER 0x64
62 #define BHI_OEMPKHASH(n) (0x64 + (0x4 * (n)))
81 #define BHIE_RXVECADDR_HIGH_OFFS 0x64
112 #define MHICTRL_RESET_MASK BIT(1)
114 #define MHISTATUS_SYSERR_MASK BIT(2)
115 #define MHISTATUS_READY_MASK BIT(0)
144 #define MHI_TRE_GET_DWORD(tre, word) le32_to_cpu((tre)->dword[(word)])
145 #define MHI_TRE_GET_CMD_CHID(tre) FIELD_GET(GENMASK(31, 24), MHI_TRE_GET_DWORD(tre, 1))
146 #define MHI_TRE_GET_CMD_TYPE(tre) FIELD_GET(GENMASK(23, 16), MHI_TRE_GET_DWORD(tre, 1))
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/openbmc/linux/include/linux/mfd/
H A Dtps65912.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/
117 #define TPS65912_VERNUM 0x64
118 #define TPS6591X_MAX_REGISTER 0x64
121 #define TPS65912_INT_STS_PWRHOLD_F BIT(0)
122 #define TPS65912_INT_STS_VMON BIT(1)
123 #define TPS65912_INT_STS_PWRON BIT(2)
124 #define TPS65912_INT_STS_PWRON_LP BIT(3)
125 #define TPS65912_INT_STS_PWRHOLD_R BIT(4)
126 #define TPS65912_INT_STS_HOTDIE BIT(5)
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/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Danalogix,anx7625.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Xin Ji <xji@analogixsemi.com>
14 The ANX7625 is an ultra-low power 4K Mobile HD Transmitter
22 maxItems: 1
26 maxItems: 1
28 enable-gpios:
30 maxItems: 1
32 reset-gpios:
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/openbmc/linux/Documentation/trace/
H A Duprobetracer.rst2 Uprobe-tracer: Uprobe-based Event Tracing
9 --------
13 Similar to the kprobe-event tracer, this doesn't need to be activated via
18 However unlike kprobe-event tracer, the uprobe event interface expects the
26 -------------------------
32 -:[GRP/][EVENT] : Clear uprobe or uretprobe event
47 $retval : Fetch return value.(\*1)
49 +|-[u]OFFS(FETCHARG) : Fetch memory at FETCHARG +|- OFFS address.(\*2)(\*3)
54 (x8/x16/x32/x64), "string" and bitfield are supported.
56 (\*1) only for return probe.
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/openbmc/linux/drivers/acpi/pmic/
H A Dintel_pmic_bytcrc.c1 // SPDX-License-Identifier: GPL-2.0
15 #define PWR_SOURCE_SELECT BIT(1)
23 .bit = ??,
28 .bit = 0x00,
29 }, /* SYSX -> VSYS_SX */
33 .bit = 0x00,
34 }, /* SYSU -> VSYS_U */
37 .reg = 0x64,
38 .bit = 0x00,
39 }, /* SYSS -> VSYS_S */
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/openbmc/linux/drivers/staging/media/atomisp/i2c/
H A Dmt9m114.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 #include <media/v4l2-subdev.h>
29 #include <media/v4l2-device.h>
30 #include <media/v4l2-ctrls.h>
31 #include <linux/v4l2-mediabus.h>
32 #include <media/media-entity.h>
42 #define MISENSOR_8BIT 1
57 #define MISENSOR_AWB_STEADY BIT(0) /* awb steady */
58 #define MISENSOR_AE_READY BIT(3) /* ae status ready */
65 #define MISENSOR_FLIP_EN 1
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/openbmc/u-boot/arch/x86/include/asm/arch-ivybridge/
H A Dpch.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Copyright (C) 2008-2009 coresystems GmbH
22 #define PCH_STEP_A1 1
33 #define MAINBOARD_POWER_ON 1
42 #define SBR (1 << 6)
43 #define SEE (1 << 1)
44 #define PERE (1 << 0)
57 #define SERIRQ_CNTL 0x64
63 #define ETR3_CWORWRE (1 << 18)
64 #define ETR3_CF9GR (1 << 20)
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/openbmc/linux/drivers/irqchip/
H A Dirq-imx-mu-msi.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * Based on drivers/mailbox/imx-mailbox.c
46 IMX_MU_V2 = BIT(1),
50 #define IMX_MU_xCR_RIEn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
51 #define IMX_MU_xSR_RFn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
73 iowrite32(val, msi_data->regs + offs); in imx_mu_write()
78 return ioread32(msi_data->regs + offs); in imx_mu_read()
86 raw_spin_lock_irqsave(&msi_data->lock, flags); in imx_mu_xcr_rmw()
87 val = imx_mu_read(msi_data, msi_data->cfg->xCR[type]); in imx_mu_xcr_rmw()
90 imx_mu_write(msi_data, val, msi_data->cfg->xCR[type]); in imx_mu_xcr_rmw()
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/openbmc/libcper/specification/document/
H A Dcper-json-specification.tex7 \title{CPER-JSON Specification}
16 \newcommand*{\thead}[1]{\multicolumn{1}{|c|}{\bfseries #1}}
17 \newcommand*{\jsontable}[1]{
19 \label{#1}
27 \newcommand*{\jsontableend}[1]{
31 \caption{#1}
32 \label{table:#1}
47 in a human-readable JSON format, intended to be interoperable with standard CPER binary.
50 …ive JSON schema\footnote{As defined by \href{https://json-schema.org/draft/2020-12/json-schema-cor…
54 \section{Parent Structure (Type 1): Full Log}
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/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dsd_emmc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
12 #define SDIO_PORT_B 1
16 #define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */
21 #define CLK_SRC_DIV2 (1 << 6)
23 #define CLK_CO_PHASE_090 (1 << 8)
27 #define CLK_TX_PHASE_090 (1 << 10)
30 #define CLK_ALWAYS_ON BIT(24)
33 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
35 #define CFG_BUS_WIDTH_4 1
44 #define CFG_SDCLK_ALWAYS_ON BIT(18)
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/openbmc/linux/sound/soc/ti/
H A Domap-dmic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * omap-dmic.h -- OMAP Digital Microphone Controller
27 #define OMAP_DMIC_FIFO_DMIC3L_DATA_REG 0x64
29 /* IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR bit fields */
30 #define OMAP_DMIC_IRQ (1 << 0)
31 #define OMAP_DMIC_IRQ_FULL (1 << 1)
32 #define OMAP_DMIC_IRQ_ALMST_EMPTY (1 << 2)
33 #define OMAP_DMIC_IRQ_EMPTY (1 << 3)
36 /* DMIC_DMAENABLE bit fields */
39 /* DMIC_CTRL bit fields */
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/openbmc/u-boot/test/
H A Dcompression.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <u-boot/zlib.h>
26 "I am a highly compressable bit of text.\n"
27 "I am a highly compressable bit of text.\n"
28 "I am a highly compressable bit of text.\n"
35 /* bzip2 -c /tmp/plain.txt > /tmp/plain.bz2 */
44 "\x18\x28\x69\xd4\x23\x64\xcc\x2b\xe5\xe8\x5f\x00\xa4\x70\x26\x2c"
47 "\xb1\x2e\x62\x7b\xab\x67\xe7\x99\x2a\x14\x5e\x9f\x64\xcb\x96\xf4"
54 /* lzma -z -c /tmp/plain.txt > /tmp/plain.lzma */
73 /* lzop -c /tmp/plain.txt > /tmp/plain.lzo */
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/openbmc/libcper/sections/
H A Dcper-section-ia32x64.c2 * Describes functions for converting IA32/x64 CPER sections from binary and JSON format
12 #include <libcper/cper-utils.h>
13 #include <libcper/sections/cper-section-ia32x64.h>
15 //Private pre-definitions.
45 //Converts the IA32/x64 error section described in the given descriptor into intermediate format.
55 //Ensure this is decoded properly in IR->CPER in cper_section_ia32x64_to_ir()
56 int processor_error_info_num = (record->ValidFields >> 2) & 0x3F; in cper_section_ia32x64_to_ir()
59 int processor_context_info_num = (record->ValidFields >> 8) & 0x3F; in cper_section_ia32x64_to_ir()
64 .value.ui64 = record->ValidFields }; in cper_section_ia32x64_to_ir()
69 json_object_new_uint64(record->ApicId)); in cper_section_ia32x64_to_ir()
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/openbmc/qemu/tests/unit/
H A Dtest-crypto-der.c28 "\x02\x01\x00" /* INTEGER, offset: 4, length: 1 */
53 "\x64\x06\x0e\xef\xe0\x6a\x5e\x6a\x41\x42\x96\x6d\xb8\x7d\xea\x95"
61 "\x02\x01\x00" /* INTEGER, offset: 4, length: 1 */
65 "\xf9\x84\x64\xdf\x87\x28\x4a\xc9\x9d\x78\x93\x47\xc8\xd9\x66\x2e"
72 "\x7f\x30\x25\x03\xd4\x3a\xff\xa2\xe8\xd6\xb5\x1f\x4f\x36\x64\x61"
87 "\x89\x72\x52\x9f\xd5\x54\xe1\x64\x52\x16\xc5\x43\x21\x56\x16\xc2"
88 "\x29\x97\x58\x00\x8d\x2f\xc5\x64\x8d\x42\x0d\x27\x21\xc6\xd1\x31"
94 "\x10\x6a\x0c\x47\xe1\xf0\x36\x70\xd2\xa7\x57\x64\x47\x46\x9f\xca"
142 "\x09\x7e\x82\xca\x91\xbe\xd0\xdd\x9c\x8c\xb0\x77\x64\x30\x1b\x7e"
152 "\x02\x01\x01" /* INTEGER, offset 2, length 1 */
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