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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmarvell,mvusb.yaml27 const: usb1286,1fa4
29 maxItems: 1
44 #address-cells = <1>;
47 mdio@1 {
48 compatible = "usb1286,1fa4";
49 reg = <1>;
50 #address-cells = <1>;
/openbmc/qemu/target/riscv/
H A Dcpu.c83 * 1. All extensions should be separated from other multi-letter extensions
258 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
375 * with the result for 'map = 1'). in satp_mode_max_from_map()
421 cpu->cfg.satp_mode.supported |= (1 << i); in set_satp_mode_max_supported()
436 cpu->cfg.satp_mode.map = (1 << VM_1_10_MBARE); in set_satp_mode_default_map()
730 cpuname = g_strsplit(cpu_model, ",", 1); in riscv_cpu_class_by_name()
873 for (j = vlenb - 1 ; j >= 0; j--) { in riscv_cpu_dump_state()
988 /* mmte is supposed to have pm.current hardwired to 1 */ in riscv_cpu_reset_hold()
992 * Bits 10, 6, 2 and 12 of mideleg are read only 1 when the Hypervisor in riscv_cpu_reset_hold()
1023 env->load_res = -1; in riscv_cpu_reset_hold()
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/openbmc/qemu/disas/
H A Driscv.c32 rv_op_lui = 1,
1000 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
1022 "0x1p-1", "0x1.4p-1", "0x1.8p-1", "0x1.cp-1",
1024 "0x1p+1", "0x1.4p+1", "0x1.8p+1", "0x1p+2",
2178 { "mop.r.1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2210 { "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2217 { "c.mop.1", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
2547 case 1: in decode_inst_opcode()
2565 case 1: in decode_inst_opcode()
2566 if (((inst >> 6) & 1) == 0) { in decode_inst_opcode()
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H A Dmips.c37 1, or (at your option) any later version.
155 #define OP_SH_PERFREG 1
371 "S" 5 bit fs source 1 register (OP_*_FS)
420 "!" 1 bit usermode flag (OP_*_MT_U)
421 "$" 1 bit load high flag (OP_*_MT_H)
424 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
429 "+1" UDI immediate bits 6-10
585 /* Broadcom SB-1 instruction. */
687 (1 != 0)
1209 1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3). $ac0 is the pair
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