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Searched +full:1 +full:c13400 (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dallwinner,suniv-f1c100s-usb-phy.yaml15 const: 1
21 maxItems: 1
28 maxItems: 1
35 maxItems: 1
42 maxItems: 1
46 maxItems: 1
73 phy@1c13400 {
81 #phy-cells = <1>;
H A Dallwinner,sun5i-a13-usb-phy.yaml15 const: 1
31 maxItems: 1
40 - description: USB Host 1 Controller reset
48 maxItems: 1
52 maxItems: 1
82 phy@1c13400 {
83 #phy-cells = <1>;
92 usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */
H A Dallwinner,sun8i-r40-usb-phy.yaml15 const: 1
38 - description: USB Host 1 PHY bus clock
49 - description: USB Host 1 Controller reset
59 maxItems: 1
63 maxItems: 1
96 phy@1c13400 {
97 #phy-cells = <1>;
H A Dallwinner,sun4i-a10-usb-phy.yaml15 const: 1
35 maxItems: 1
44 - description: USB Host 1 Controller reset
54 maxItems: 1
58 maxItems: 1
91 usbphy: phy@1c13400 {
92 #phy-cells = <1>;
/openbmc/u-boot/doc/device-tree-bindings/phy/
H A Dsun4i-usb-phy.txt23 - #phy-cells : from the generic phy bindings, must be 1
48 usbphy: phy@01c13400 {
49 #phy-cells = <1>;
56 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsuniv-f1c100s.dtsi11 #address-cells = <1>;
12 #size-cells = <1>;
32 #address-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <1>;
48 sram-controller@1c00000 {
52 #address-cells = <1>;
53 #size-cells = <1>;
59 #address-cells = <1>;
60 #size-cells = <1>;
[all …]
H A Dsun5i.dtsi51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
67 #address-cells = <1>;
68 #size-cells = <1>;
92 #address-cells = <1>;
93 #size-cells = <1>;
112 #address-cells = <1>;
113 #size-cells = <1>;
128 #address-cells = <1>;
[all …]
H A Dsun4i-a10.dtsi50 #address-cells = <1>;
51 #size-cells = <1>;
59 #address-cells = <1>;
60 #size-cells = <1>;
110 #address-cells = <1>;
161 #address-cells = <1>;
162 #size-cells = <1>;
192 #address-cells = <1>;
193 #size-cells = <1>;
208 #address-cells = <1>;
[all …]
H A Dsun8i-r40.dtsi54 #address-cells = <1>;
55 #size-cells = <1>;
59 #address-cells = <1>;
60 #size-cells = <1>;
81 #address-cells = <1>;
93 cpu1: cpu@1 {
96 reg = <1>;
163 thermal-sensors = <&ths 1>;
169 #address-cells = <1>;
170 #size-cells = <1>;
[all …]
H A Dsun7i-a20.dtsi54 #address-cells = <1>;
55 #size-cells = <1>;
62 #address-cells = <1>;
63 #size-cells = <1>;
100 #address-cells = <1>;
121 cpu1: cpu@1 {
124 reg = <1>;
174 #address-cells = <1>;
175 #size-cells = <1>;
203 #address-cells = <1>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsun8i-r40.dtsi49 #address-cells = <1>;
50 #size-cells = <1>;
54 #address-cells = <1>;
55 #size-cells = <1>;
74 #address-cells = <1>;
83 cpu@1 {
86 reg = <1>;
104 #address-cells = <1>;
105 #size-cells = <1>;
108 nmi_intc: interrupt-controller@1c00030 {
[all …]
H A Dsun5i.dtsi55 #address-cells = <1>;
67 #address-cells = <1>;
68 #size-cells = <1>;
80 framebuffer@1 {
92 #address-cells = <1>;
93 #size-cells = <1>;
96 osc24M: clk@1c20050 {
111 soc@1c00000 {
113 #address-cells = <1>;
114 #size-cells = <1>;
[all …]
H A Dsun4i-a10.dtsi50 #address-cells = <1>;
51 #size-cells = <1>;
59 #address-cells = <1>;
60 #size-cells = <1>;
110 #address-cells = <1>;
162 #address-cells = <1>;
163 #size-cells = <1>;
189 #address-cells = <1>;
190 #size-cells = <1>;
193 sram-controller@1c00000 {
[all …]
H A Dsun7i-a20.dtsi61 #address-cells = <1>;
62 #size-cells = <1>;
76 framebuffer@1 {
99 #address-cells = <1>;
121 cpu@1 {
124 reg = <1>;
179 #address-cells = <1>;
180 #size-cells = <1>;
183 osc24M: clk@1c20050 {
206 mii_phy_tx_clk: clk@1 {
[all …]