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/openbmc/openbmc/meta-openembedded/meta-networking/recipes-support/netperf/
H A Dnetperf_git.bb15 file://0001-netlib.c-Move-including-sched.h-out-og-function.patch \
16 file://0001-nettest_omni-Remove-duplicate-variable-definitions.patch \
18 file://0001-Makefile.am-add-ACLOCAL_AMFLAGS.patch \
19 file://0001-Fix-too-many-arguments-error-occurring-in-gcc-15.patch \
26 inherit update-rc.d autotools texinfo systemd
29 CFLAGS:append = " -DDO_UNIX -DDO_IPV6 -D_GNU_SOURCE"
33 CFLAGS:append = " -D_FILE_OFFSET_BITS=64"
36 PACKAGECONFIG[sctp] = "--enable-sctp,--disable-sctp,lksctp-tools,"
37 PACKAGECONFIG[intervals] = "--enable-intervals,--disable-intervals,,"
38 PACKAGECONFIG[histogram] = "--enable-histogram,--disable-histogram,,"
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/openbmc/openbmc/poky/scripts/contrib/
H A Dpatchreview.py5 # SPDX-License-Identifier: GPL-2.0-only
22 # - option to just list all broken files
23 # - test suite
24 # - validate signed-off-by
26 … = ("accepted", "pending", "inappropriate", "backport", "submitted", "denied", "inactive-upstream")
29 # Whether the patch has an Upstream-Status or not
31 # If the Upstream-Status tag is malformed in some way (string for bad bit)
33 # If the Upstream-Status value is unknown (boolean)
37 # Whether the patch has a Signed-off-by or not
39 # Whether the Signed-off-by tag is malformed in some way
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/openbmc/openbmc/meta-arm/ci/
H A Dpatchreview3 # SPDX-License-Identifier: GPL-2.0-only
7 # - option to just list all broken files
8 # - test suite
9 # - validate signed-off-by
29 # Whether the patch has an Upstream-Status or not
31 # If the Upstream-Status tag is malformed in some way (string for bad bit)
33 # If the Upstream-Status value is unknown (boolean)
37 # Whether the patch has a Signed-off-by or not
39 # Whether the Signed-off-by tag is malformed in some way
41 # The Signed-off-by tag value
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/openbmc/openbmc/poky/scripts/contrib/bb-perf/
H A Dbuildstats-plot.sh5 # SPDX-License-Identifier: GPL-2.0-or-later
10 # depending if either the -S parameter is present or not:
12 # * without -S: Produces a histogram listing top N recipes/tasks versus
13 # stats. The first stat defined in the -s parameter is the one taken
15 # * -S: Produces a histogram listing tasks versus stats. In this case,
17 # Stats values are in descending order defined by the first stat defined on -s
21 # 1. Top recipes' tasks taking into account utime
23 # $ buildstats-plot.sh -s utime | gnuplot -p
27 # $ buildstats-plot.sh -s utime:stime -S | gnuplot -p
31 # $ buildstats-plot.sh -s 'IO write_bytes:IO read_bytes' -S | gnuplot -p
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/openbmc/qemu/target/xtensa/core-de212/
H A Dcore-isa.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2015 Tensilica Inc.
39 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
44 /*----------------------------------------------------------------------
46 ----------------------------------------------------------------------*/
48 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
49 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
53 #define XCHAL_HAVE_DEBUG 1 /* debug option */
54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
55 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
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/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2016 Tensilica Inc.
39 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
44 /*----------------------------------------------------------------------
46 ----------------------------------------------------------------------*/
48 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
49 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
53 #define XCHAL_HAVE_DEBUG 1 /* debug option */
54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
55 #define XCHAL_HAVE_LOOPS 0 /* zero-overhead loops */
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/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2020 Tensilica Inc.
34 //depot/dev/Homewood/Xtensa/SWConfig/hal/core-common.h.tph#24 - edit change 444323 (text+ko)
41 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
46 /*----------------------------------------------------------------------
48 ----------------------------------------------------------------------*/
50 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
51 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
55 #define XCHAL_HAVE_DEBUG 1 /* debug option */
56 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
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/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2015 Tensilica Inc.
39 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
44 /*----------------------------------------------------------------------
46 ----------------------------------------------------------------------*/
48 #define XCHAL_HAVE_BE 1 /* big-endian byte ordering */
49 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
53 #define XCHAL_HAVE_DEBUG 1 /* debug option */
54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
55 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
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/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Copyright (C) 1999-2015 Tensilica Inc.
18 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
23 /*----------------------------------------------------------------------
25 ----------------------------------------------------------------------*/
27 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
28 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
32 #define XCHAL_HAVE_DEBUG 1 /* debug option */
33 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
34 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
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/openbmc/qemu/target/hexagon/imported/mmvec/
H A Dext.idef2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
26 #define __SELF_DEF_EXTINSN 1
148 * MMVECTOR MEMORY OPERATIONS - NO NAPALI V1
215 DSTM(1,VdV.SRCTYPE[i],SATFUNC(RNDFUNC(VuV.SRCTYPE[i],shamt) >> shamt)))
308 * MMVECTOR MEMORY OPERATIONS - NON TEMPORAL
314 MMVEC_EACH_EA(vS32b_nt,"Aligned Vector Store - Non temporal",ATTRIBS(ATTR_VMEM_NT,A_STORE,A_RESTRIC…
315 MMVEC_COND_EACH_EA(vS32b_nt,"Aligned Vector Store - Non temporal",ATTRIBS(ATTR_VMEM_NT,A_STORE,A_RE…
317 MMVEC_EACH_EA(vS32b_nt_new,"Aligned Vector Store New - Non temporal",ATTRIBS(ATTR_VMEM_NT,A_STORE,A…
318 MMVEC_COND_EACH_EA(vS32b_nt_new,"Aligned Vector Store New - Non temporal",ATTRIBS(ATTR_VMEM_NT,A_ST…
321 MMVEC_STQ(vS32b_nt, "Aligned Vector Store - Non temporal", ATTRIBS(ATTR_VMEM_NT,A_STORE,A_RES…
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/openbmc/qemu/hw/intc/
H A Dxive.c4 * Copyright (c) 2017-2018, IBM Corporation.
6 * SPDX-License-Identifier: GPL-2.0-or-later
17 #include "hw/qdev-properties.h"
34 if (!(tctx->regs[cur_ring + TM_WORD2] & 0x80)) { in xive_ring_valid()
87 return tctx->os_output; in xive_tctx_output()
90 return tctx->hv_output; in xive_tctx_output()
102 uint8_t *sig_regs = &tctx->regs[sig_ring]; in xive_tctx_accept()
107 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_NSR] == 0); in xive_tctx_accept()
108 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] == 0); in xive_tctx_accept()
109 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0); in xive_tctx_accept()
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/openbmc/qemu/target/hexagon/
H A Dop_helper.c2 * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.
20 #include "accel/tcg/cpu-ldst.h"
22 #include "exec/helper-proto.h"
44 qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception); in hexagon_raise_exception_err()
45 cs->exception_index = exception; in hexagon_raise_exception_err()
57 env->mem_log_stores[slot].va = addr; in log_store32()
58 env->mem_log_stores[slot].width = width; in log_store32()
59 env->mem_log_stores[slot].data32 = val; in log_store32()
65 env->mem_log_stores[slot].va = addr; in log_store64()
66 env->mem_log_stores[slot].width = width; in log_store64()
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/openbmc/qemu/target/arm/tcg/
H A Dsve.decode26 %imm6_22_5 22:1 5:5
32 %index3_22_19 22:1 19:2
33 %index3_22_17 22:1 17:2
34 %index3_19_11 19:2 11:1
35 %index2_20_11 20:1 11:1
37 # A combination of tsz:imm3 -- extract esize.
39 # A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3)
41 # A combination of tsz:imm3 -- extract (tsz:imm3) - esize
49 # Signed 8-bit immediate, optionally shifted left by 8.
51 # Unsigned 8-bit immediate, optionally shifted left by 8.
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/openbmc/qemu/scripts/
H A Dcheckpatch.pl5 # (c) 2008-2010 Andy Whitcroft <apw@canonical.com>
22 my $tree = 1;
23 my $chk_signoff = 1;
32 my $summary = 1;
49 $P [OPTION]... [GIT-REV-LIST]
54 -q, --quiet quiet
55 --no-tree run without a qemu tree
56 --no-signoff do not check for 'Signed-off-by' line
57 --patch treat FILE as patchfile
58 --branch treat args as GIT revision list
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