Searched +full:100 +full:base +full:- +full:fx +full:- +full:to +full:- +full:100 +full:base +full:- +full:tx (Results 1 – 17 of 17) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)4 ---6 $schema: http://devicetree.org/meta-schemas/core.yaml#11 - $ref: ethernet-phy.yaml#14 - Andrew Davis <afd@ti.com>17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and20 100BASE-FX Fiber protocols.21 This device interfaces to the MAC layer through Reduced GMII (RGMII) and[all …]
1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)4 ---6 $schema: http://devicetree.org/meta-schemas/core.yaml#11 - Andrew Davis <afd@ti.com>14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It15 provides all of the physical layer functions needed to transmit and receive16 data over standard, twisted-pair cables or to connect to an external,17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to18 connect to a MAC through a standard MII, RMII, or RGMII interface24 - $ref: ethernet-phy.yaml#[all …]
1 // SPDX-License-Identifier: GPL-2.0-only12 [NETIF_F_SG_BIT] = "tx-scatter-gather",13 [NETIF_F_IP_CSUM_BIT] = "tx-checksum-ipv4",14 [NETIF_F_HW_CSUM_BIT] = "tx-checksum-ip-generic",15 [NETIF_F_IPV6_CSUM_BIT] = "tx-checksum-ipv6",17 [NETIF_F_FRAGLIST_BIT] = "tx-scatter-gather-fraglist",18 [NETIF_F_HW_VLAN_CTAG_TX_BIT] = "tx-vlan-hw-insert",20 [NETIF_F_HW_VLAN_CTAG_RX_BIT] = "rx-vlan-hw-parse",21 [NETIF_F_HW_VLAN_CTAG_FILTER_BIT] = "rx-vlan-filter",22 [NETIF_F_HW_VLAN_STAG_TX_BIT] = "tx-vlan-stag-hw-insert",[all …]
1 .. SPDX-License-Identifier: GPL-2.018 Please report problems to one or more of:20 - Andrew Morton21 - Netdev mailing list <netdev@vger.kernel.org>22 - Linux kernel mailing list <linux-kernel@vger.kernel.org>28 Since kernel 2.3.99-pre6, this driver incorporates the support for the29 3c575-series Cardbus cards which used to be handled by 3c575_cb.c.33 - 3c590 Vortex 10Mbps34 - 3c592 EISA 10Mbps Demon/Vortex35 - 3c597 EISA Fast Demon/Vortex[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * Copyright 2010-2011 Freescale Semiconductor, Inc.11 /* Broadcom BCM54xx -- taken from linux sungem_phy */62 * bit[8] RGMII RXD to RXC skew in bcm5461_config()69 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in bcm5461_config()70 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) in bcm5461_config()75 * TX interface delay: reg 0x1c, shadow value b'0011: clock alignment control in bcm5461_config()83 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in bcm5461_config()84 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) in bcm5461_config()102 phydev->duplex = DUPLEX_HALF; in bcm54xx_parse_status()[all …]
1 // SPDX-License-Identifier: GPL-2.0+13 #include "bcm-phy-lib.h"25 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)28 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))43 struct bcm54xx_phy_priv *priv = phydev->priv; in bcm54xx_phy_can_wakeup()45 return phy_interrupt_is_valid(phydev) || priv->wake_irq >= 0; in bcm54xx_phy_can_wakeup()55 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || in bcm54xx_config_clock_delay()56 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { in bcm54xx_config_clock_delay()57 /* Disable RGMII RXC-RXD skew */ in bcm54xx_config_clock_delay()60 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in bcm54xx_config_clock_delay()[all …]
1 // SPDX-License-Identifier: GPL-2.016 #include <dt-bindings/net/ti-dp83869.h>70 /* This is the same bit mask as the BMCR so re-use the BMCR default */158 struct dp83869_private *dp83869 = phydev->priv; in dp83869_read_status()165 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) { in dp83869_read_status()166 if (phydev->link) { in dp83869_read_status()167 if (dp83869->mode == DP83869_RGMII_100_BASE) in dp83869_read_status()168 phydev->speed = SPEED_100; in dp83869_read_status()170 phydev->speed = SPEED_UNKNOWN; in dp83869_read_status()171 phydev->duplex = DUPLEX_UNKNOWN; in dp83869_read_status()[all …]
3 Written 1999-2000 by Donald Becker.5 This software may be used and distributed according to the terms of19 [link no longer provides useful info -jgarzik]27 /* The user-configurable values.30 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).34 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.35 Setting to > 1518 effectively disables this feature.37 need a copy-align. */45 100mbps_hd 100Mbps half duplex.46 100mbps_fd 100Mbps full duplex.[all …]
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3 Written 2002-2004 by David Dillow <dave@thedillows.org>4 Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and7 This software may be used and distributed according to the terms of17 pursuant to 15 C.F.R. Section 740.13(e).21 number Y1-LM-2015-01.27 *) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware29 *) Waiting for a command response takes 8ms due to non-preemptable37 *) Fix MAC changing to work while the interface is up38 (Need to put commands on the TX ring, which changes40 *) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See[all …]
3 Written 1996-1999 by Donald Becker.5 This software may be used and distributed according to the terms12 Problem reports and questions should be directed to27 * due to dead code elimination. There will be some performance benefits from this due to43 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.44 Setting to > 1512 effectively disables this feature. */48 /* ARM systems perform better by disregarding the bus-master49 transfer capability of these cards. -- rmk */52 /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */[all …]
2 Written 1997-1998 by Donald Becker.4 This software may be used and distributed according to the terms15 2000/2/2- Added support for kernel-level ISAPnP19 2001/11/17 - Added ethtool support (jgarzik)21 2002/10/28 - Locking updates for 2.5 (alan@lxorguk.ukuu.org.uk)30 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.31 Setting to > 1512 effectively disables this feature. */34 /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */37 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */40 /* Enable the automatic media selection code -- usually set. */[all …]
3 * Copyright 1996-1999 Thomas Bogendoerfer10 * This software may be used and distributed according to the terms17 * Fixed a few bugs, related to running the controller in 32bit mode.85 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */109 * table to translate option values from tulip110 * to internal options113 PCNET32_PORT_ASEL, /* 0 Auto-select */117 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */123 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */126 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */[all …]
3 Written/copyright 1999-2001 by Donald Becker.8 This software may be used and distributed according to the terms of23 [link no longer provides useful info -jgarzik]62 /* Updated to recommendations in pci-skeleton v2.03. */64 /* The user-configurable values.72 static int debug = -1;76 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).78 static const int multicast_filter_limit = 100;80 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.81 Setting to > 1518 effectively disables this feature. */[all …]
1 /* Copyright 2008-2013 Broadcom Corporation6 * agreement governing use of this software, this software is licensed to you8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)205 (_phy)->def_md_devad, \211 (_phy)->def_md_devad, \239 * bnx2x_check_lfa - This function checks if link reinitialization is required,251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()257 /* NOTE: must be first condition checked - in bnx2x_check_lfa()[all …]
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)19 #include <dt-bindings/net/mscc-phy-vsc8531.h>125 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_sset_count()130 return priv->nstats; in vsc85xx_get_sset_count()135 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_strings()141 for (i = 0; i < priv->nstats; i++) in vsc85xx_get_strings()142 strscpy(data + i * ETH_GSTRING_LEN, priv->hw_stats[i].string, in vsc85xx_get_strings()148 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_stat()151 val = phy_read_paged(phydev, priv->hw_stats[i].page, in vsc85xx_get_stat()152 priv->hw_stats[i].reg); in vsc85xx_get_stat()[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later7 * https://github.com/microchip-ung/sparx-5_reginfo9 …* https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Swi…104 u8 if_width; /* UDL if-width: 10/16/20/32/64 */107 bool no_pwrcycle:1; /* Omit initial power-cycle */113 u8 duty_cycle; /* Set output level to half/full */241 u8 duty_cycle; /* Set output level to half/full */246 bool no_pwrcycle:1; /* Omit initial power-cycle */249 bool txmargin:1; /* Set output level to half/full */616 /* map from SD25G28 interface width to configuration value */[all …]