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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/crucible/
H A Dcrucible-go-mods.inc2 …gomod://cloud.google.com/go;version=v0.111.0;sha256sum=f17610c7b09a9582375daa59ec73761b0bd7ad31307…
3 …gomod://cloud.google.com/go;version=v0.26.0;mod=1;sha256sum=2218a34f20b971bc195216d4195f57520a2acb…
5 …gomod://cloud.google.com/go/compute/metadata;version=v0.2.3;sha256sum=292864dbd0b1de37a968e285e949…
8 …gomod://cloud.google.com/go/longrunning;version=v0.5.4;sha256sum=a3eb14ee47bfdbca7df05c0011bcd9a86…
10 …gomod://github.com/BurntSushi/toml;version=v0.3.1;mod=1;sha256sum=28021b4180a59c3993607a95b18e230d…
11 …gomod://github.com/census-instrumentation/opencensus-proto;version=v0.2.1;mod=1;sha256sum=dae64639…
12 …gomod://github.com/client9/misspell;version=v0.3.4;mod=1;sha256sum=d1bc362dddd96fb3a43ed4b92aaab70…
13 …gomod://github.com/cncf/udpa/go;version=v0.0.0-20191209042840-269d4d468f6f;mod=1;sha256sum=05f5d4a…
14 …gomod://github.com/davecgh/go-spew;version=v1.1.0;mod=1;sha256sum=bcb29393251237b79a17b6c19bf29134…
15 …gomod://github.com/davecgh/go-spew;version=v1.1.1;mod=1;sha256sum=bcb29393251237b79a17b6c19bf29134…
[all …]
/openbmc/linux/arch/arm64/crypto/
H A Daes-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aesce-ccm-core.S - AES-CCM transform for ARMv8 with Crypto Extensions
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
12 .arch armv8-a+crypto
19 ld1 {v0.16b}, [x0] /* load mac */
20 cbz w3, 1f
23 0: ldrb w7, [x1], #1 /* get 1 byte of input */
24 subs w2, w2, #1
25 add w3, w3, #1
27 ext v1.16b, v1.16b, v1.16b, #1 /* rotate in the input bytes */
[all …]
H A Daes-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
9 .arch armv8-a+crypto
13 ld1 {v0.16b}, [x2]
22 1: aese v0.16b, v2.16b
23 aesmc v0.16b, v0.16b
25 aese v0.16b, v3.16b
26 aesmc v0.16b, v0.16b
29 aese v0.16b, v1.16b
30 aesmc v0.16b, v0.16b
[all …]
H A Dsm4-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
13 #include "sm4-ce-asm.h"
15 .arch armv8-a+crypto
17 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
45 * x0: 128-bit key
51 ld1 {v0.16b}, [x0];
52 rev32 v0.16b, v0.16b;
55 ld1 {v24.16b-v27.16b}, [x4], #64;
56 ld1 {v28.16b-v31.16b}, [x4];
[all …]
H A Daes-modes.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm64/crypto/aes-modes.S - chaining mode wrappers for AES
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
8 /* included by aes-ce.S and aes-neon.S */
26 encrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
31 decrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
37 encrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
42 decrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
62 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
66 st1 {v0.16b-v3.16b}, [x0], #64
[all …]
H A Dsm4-ce-gcm-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * SM4-GCM AEAD Algorithm using ARMv8 Crypto Extensions
14 #include "sm4-ce-asm.h"
16 .arch armv8-a+crypto
18 .irp b, 0, 1, 2, 3, 24, 25, 26, 27, 28, 29, 30, 31
37 * output: r0:r1 (low 128-bits in r0, high in r1)
41 pmull r0.1q, m0.1d, m1.1d; \
42 pmull T1.1q, m0.1d, T0.1d; \
43 pmull2 T0.1q, m0.2d, T0.2d; \
44 pmull2 r1.1q, m0.2d, m1.2d; \
[all …]
H A Dsm4-neon-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
35 ld1 {v16.16b-v19.16b}, [x5], #64; \
36 ld1 {v20.16b-v23.16b}, [x5], #64; \
37 ld1 {v24.16b-v27.16b}, [x5], #64; \
38 ld1 {v28.16b-v31.16b}, [x5];
103 /* sbox, non-linear part */ \
105 tbl RTMP0.16b, {v16.16b-v19.16b}, RX0.16b; \
107 tbx RTMP0.16b, {v20.16b-v23.16b}, RX0.16b; \
109 tbx RTMP0.16b, {v24.16b-v27.16b}, RX0.16b; \
[all …]
/openbmc/linux/arch/mips/include/asm/mach-cavium-octeon/
H A Dkernel-entry-init.h6 * Copyright (C) 2005-2008 Cavium Networks, Inc
14 #define CP0_DCACHE_ERR_REG $27, 1
25 # a2 = 1 if init core, zero otherwise
30 dmfc0 v0, CP0_CVMMEMCTL_REG
32 dins v0, $0, 0, 6
33 ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
34 dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
35 dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
38 or v0, v0, 0x5001
39 xor v0, v0, 0x1001
[all …]
/openbmc/linux/tools/testing/selftests/powerpc/math/
H A Dvmx_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 # Should be safe from C, only touches r4, r5 and v0,v1,v2
13 li r3,1 # assume a bad result
15 lvx v0,r5,r4
16 vcmpequd. v1,v0,v20
20 lvx v0,r5,r4
21 vcmpequd. v1,v0,v21
25 lvx v0,r5,r4
26 vcmpequd. v1,v0,v22
30 lvx v0,r5,r4
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler_gfx10.asm26 * cpp -DASIC_FAMILY=CHIP_NAVI10 cwsr_trap_handler_gfx10.asm -P -o nv1x.sp3
27 * sp3 nv1x.sp3 -hex nv1x.hex
30 * cpp -DASIC_FAMILY=CHIP_SIENNA_CICHLID cwsr_trap_handler_gfx10.asm -P -o gfx10.sp3
31 * sp3 gfx10.sp3 -hex gfx10.hex
34 * cpp -DASIC_FAMILY=CHIP_PLUM_BONITO cwsr_trap_handler_gfx10.asm -P -o gfx11.sp3
35 * sp3 gfx11.sp3 -hex gfx11.hex
48 var SINGLE_STEP_MISSED_WORKAROUND = 1 //workaround for lost MODE.DEBUG_EN exception when SAVECTX r…
61 var SQ_WAVE_IB_STS2_WAVE64_SIZE = 1
221 // Let second-level handle non-SAVECTX exception or trap.
222 // Any concurrent SAVECTX will be handled upon re-entry once halted.
[all …]
/openbmc/linux/arch/powerpc/crypto/
H A Dcrc32-vpmsum_core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 * 32 bits of 0s to the end - this matches what a CRC does. We just
28 #include <asm/ppc-opcode.h>
66 std r31,-8(r1)
67 std r30,-16(r1)
68 std r29,-24(r1)
69 std r28,-32(r1)
70 std r27,-40(r1)
71 std r26,-48(r1)
72 std r25,-56(r1)
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/device/
H A Dctrl.c38 struct nvif_control_pstate_info_v0 v0; in nvkm_control_mthd_pstate_info() member
40 struct nvkm_clk *clk = ctrl->device->clk; in nvkm_control_mthd_pstate_info()
41 int ret = -ENOSYS; in nvkm_control_mthd_pstate_info()
43 nvif_ioctl(&ctrl->object, "control pstate info size %d\n", size); in nvkm_control_mthd_pstate_info()
44 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { in nvkm_control_mthd_pstate_info()
45 nvif_ioctl(&ctrl->object, "control pstate info vers %d\n", in nvkm_control_mthd_pstate_info()
46 args->v0.version); in nvkm_control_mthd_pstate_info()
51 args->v0.count = clk->state_nr; in nvkm_control_mthd_pstate_info()
52 args->v0.ustate_ac = clk->ustate_ac; in nvkm_control_mthd_pstate_info()
53 args->v0.ustate_dc = clk->ustate_dc; in nvkm_control_mthd_pstate_info()
[all …]
H A Duser.c51 return -EINVAL; in nvkm_udevice_info_subdev()
57 return -ENODEV; in nvkm_udevice_info_subdev()
64 if (args->mthd & NV_DEVICE_INFO_UNIT) { in nvkm_udevice_info_v1()
65 if (nvkm_udevice_info_subdev(device, args->mthd, &args->data)) in nvkm_udevice_info_v1()
66 args->mthd = NV_DEVICE_INFO_INVALID; in nvkm_udevice_info_v1()
69 args->mthd = NV_DEVICE_INFO_INVALID; in nvkm_udevice_info_v1()
75 struct nvkm_object *object = &udev->object; in nvkm_udevice_info()
76 struct nvkm_device *device = udev->device; in nvkm_udevice_info()
77 struct nvkm_fb *fb = device->fb; in nvkm_udevice_info()
78 struct nvkm_instmem *imem = device->imem; in nvkm_udevice_info()
[all …]
/openbmc/qemu/tests/tcg/aarch64/
H A Dtest-aes.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include "../multiarch/test-aes-main.c.inc"
8 asm("ld1 { v0.16b }, [%1]\n\t" in test_SB_SR()
10 "aese v0.16b, v1.16b\n\t" in test_SB_SR()
11 "st1 { v0.16b }, [%0]" in test_SB_SR()
12 : : "r"(o), "r"(i) : "v0", "v1", "memory"); in test_SB_SR()
18 asm("ld1 { v0.16b }, [%1]\n\t" in test_MC()
19 "aesmc v0.16b, v0.16b\n\t" in test_MC()
20 "st1 { v0.16b }, [%0]" in test_MC()
21 : : "r"(o), "r"(i) : "v0", "memory"); in test_MC()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/core/
H A Dioctl.c37 struct nvif_ioctl_nop_v0 v0; in nvkm_ioctl_nop() member
39 int ret = -ENOSYS; in nvkm_ioctl_nop()
42 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { in nvkm_ioctl_nop()
43 nvif_ioctl(object, "nop vers %lld\n", args->v0.version); in nvkm_ioctl_nop()
44 args->v0.version = NVIF_VERSION_LATEST; in nvkm_ioctl_nop()
55 if ( object->func->uevent && in nvkm_ioctl_sclass_()
56 !object->func->uevent(object, NULL, 0, NULL) && index-- == 0) { in nvkm_ioctl_sclass_()
57 oclass->ctor = nvkm_uevent_new; in nvkm_ioctl_sclass_()
58 oclass->base.minver = 0; in nvkm_ioctl_sclass_()
59 oclass->base.maxver = 0; in nvkm_ioctl_sclass_()
[all …]
/openbmc/qemu/tests/tcg/hexagon/
H A Dscatter_gather.c2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
24 * _16 16-bit elements and 16-bit offsets
25 * _32 32-bit elements and 32-bit offsets
26 * _16_32 16-bit elements and 32-bit offsets
51 /* fake vtcm - put buffers together and force alignment */
89 #define SYNC_VECTOR 1
226 asm ("m0 = %1\n\t" in vector_scatter_16()
227 "v0 = vmem(%2 + #0)\n\t" in vector_scatter_16()
229 "vscatter(%0, m0, v0.h).h = v1\n\t" in vector_scatter_16()
232 : "m0", "v0", "v1", "memory"); in vector_scatter_16()
[all …]
/openbmc/linux/lib/
H A Dsiphash.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 /* Copyright (C) 2016-2022 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
4 * SipHash: a fast short-input PRF
7 * This implementation is specifically for SipHash2-4 for a secure PRF
8 * and HalfSipHash1-3/SipHash1-3 for an insecure PRF only suitable for
17 #include <asm/word-at-a-time.h>
20 #define SIPROUND SIPHASH_PERMUTATION(v0, v1, v2, v3)
23 u64 v0 = SIPHASH_CONST_0; \
28 v3 ^= key->key[1]; \
29 v2 ^= key->key[0]; \
[all …]
/openbmc/linux/arch/mips/kernel/
H A Dscall32-o32.S6 * Copyright (C) 1995-99, 2000- 02, 06 Ralf Baechle <ralf@linux-mips.org>
22 #include <asm/asm-offsets.h>
51 bltz t4, bad_stack # -> sp is bad
81 * syscall number is in v0 unless we called syscall(__NR_###)
84 subu t2, v0, __NR_O32_Linux
85 bnez t2, 1f /* __NR_syscall at offset 0 */
88 1:
89 LONG_S v0, TI_SYSCALL($28) # Save v0 as syscall number
95 bnez t0, syscall_trace_entry # -> yes
97 subu v0, v0, __NR_O32_Linux # check syscall number
[all …]
H A Dbmips_5xxx_init.S7 * Copyright (C) 2011-2012 by Broadcom Corporation
31 subu t2, linesize, 1 ; \
34 addiu t1, t1, -1 ; \
59 #define CP0_BRCM_MODE $22, 1
63 #define CP0_ICACHE_DATA_LO $28, 1
67 #define CP0_ICACHE_DATA_HI $29, 1
70 #define CP0_BRCM_MODE_Luc_MASK (1 << 11)
71 #define CP0_BRCM_CONFIG0_CWF_MASK (1 << 20)
72 #define CP0_BRCM_CONFIG0_TSE_MASK (1 << 19)
73 #define CP0_BRCM_MODE_SET_MASK (1 << 7)
[all …]
H A Dscall64-o32.S6 * Copyright (C) 1995 - 2000, 2001 by Ralf Baechle
13 * to ABI64 calling convention. 64-bit syscalls are also processed
36 dsubu t0, v0, __NR_O32_Linux # check syscall number
43 move a1, v0
83 * absolute syscall number is in v0 unless we called syscall(__NR_###)
86 * only defined when compiling with -mabi=32 (CONFIG_32BIT)
90 subu t2, v0, __NR_O32_Linux
91 bnez t2, 1f /* __NR_syscall at offset 0 */
94 1:
95 LONG_S v0, TI_SYSCALL($28) # Save v0 as syscall number
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D085.out2 Formatting 'TEST_DIR/t.IMGFMT.1', fmt=IMGFMT size=134217728
15 { 'execute': 'blockdev-snapshot-sync',
17 'snapshot-file':'TEST_DIR/1-snapshot-v0.IMGFMT',
19 …TEST_DIR/1-snapshot-v0.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib …
22 === Invalid command - missing device and nodename ===
24 { 'execute': 'blockdev-snapshot-sync',
25 'arguments': { 'snapshot-file':'TEST_DIR/1-snapshot-v0.IMGFMT',
27 {"error": {"class": "GenericError", "desc": "Cannot find device='' nor node-name=''"}}
29 === Invalid command - missing snapshot-file ===
31 { 'execute': 'blockdev-snapshot-sync',
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/pm/
H A Dbase.c41 list_for_each_entry(dom, &pm->domains, head) in nvkm_pm_count_perfdom()
53 for (i = 0; i < dom->signal_nr; i++) { in nvkm_perfdom_count_perfsig()
54 if (dom->signal[i].name) in nvkm_perfdom_count_perfsig()
67 list_for_each_entry(dom, &pm->domains, head) { in nvkm_perfdom_find()
86 if (!dom->signal[si].name) in nvkm_perfsig_find()
88 return &dom->signal[si]; in nvkm_perfsig_find()
96 for (i = 0; i < ARRAY_SIZE(sig->source); i++) { in nvkm_perfsig_count_perfsrc()
97 if (sig->source[i]) in nvkm_perfsig_count_perfsrc()
108 int tmp = 1; /* Sources ID start from 1 */ in nvkm_perfsrc_find()
111 for (i = 0; i < ARRAY_SIZE(sig->source) && sig->source[i]; i++) { in nvkm_perfsrc_find()
[all …]
/openbmc/linux/tools/testing/selftests/netfilter/
H A Drpath.sh2 # SPDX-License-Identifier: GPL-2.0
8 if iptables-legacy --version >/dev/null 2>&1; then
9 iptables='iptables-legacy'
10 elif iptables --version >/dev/null 2>&1; then
16 if ip6tables-legacy --version >/dev/null 2>&1; then
17 ip6tables='ip6tables-legacy'
18 elif ip6tables --version >/dev/null 2>&1; then
24 if nft --version >/dev/null 2>&1; then
30 if [ -z "$iptables$ip6tables$nft" ]; then
35 sfx=$(mktemp -u "XXXXXXXX")
[all …]
/openbmc/linux/arch/mips/lib/
H A Dstrncpy_user.S12 #include <asm/asm-offsets.h>
22 * Returns: -EFAULT if exception before terminator, N if the entire
38 1: EX(lbue, v0, (v1), .Lfault)
41 1: EX(lbu, v0, (v1), .Lfault)
43 PTR_ADDIU v1, 1
45 sb v0, (a0)
46 beqz v0, 2f
47 PTR_ADDIU t0, 1
48 PTR_ADDIU a0, 1
49 bne t0, a2, 1b
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/
H A Dlowlevel_init_luton.S1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
12 #define BIT(nr) (1 << (nr))
24 lw v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0
25 andi v1, v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS
26 bne v1, zero, 1f
43 2: lw v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0
44 andi v1, v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS
50 1: lw v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0
54 and v0, v0, v1
57 ori v0, v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV_ENC(6)
[all …]

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