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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dintel,lgm-emmc-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Lightning Mountain(LGM) eMMC PHY
10 - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
13 Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon
14 node is used to reference the base address of eMMC phy registers.
16 The eMMC PHY node should be the child of a syscon node with the
19 - compatible: Should be one of the following:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dallwinner,sun4i-a10-mmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/allwinner,sun4i-a10-mmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: mmc-controller.yaml
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
17 "#address-cells": true
18 "#size-cells": true
22 - const: allwinner,sun4i-a10-mmc
[all …]
H A Dmarvell,xenon-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 mmc-controller.yaml and the properties used by the Xenon implementation.
20 - Ulf Hansson <ulf.hansson@linaro.org>
25 - enum:
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
29 - items:
[all …]
H A Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
26 const: 1
30 "#size-cells":
37 broken-cd:
42 cd-gpios:
[all …]
H A Dmmc-pwrseq-emmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-emmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple eMMC hardware reset provider
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 The purpose of this driver is to perform standard eMMC hw reset
16 fix possible issues if bootloader has left eMMC card in initialized or
19 doesn't have hardware reset logic connected to emmc card and (limited or
20 broken) ROM bootloaders are unable to read second stage from the emmc
[all …]
/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxl-s905x-libretech-cc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/sound/meson-aiu.h>
13 #include "meson-gxl-s905x.dtsi"
16 compatible = "libretech,aml-s905x-cc", "amlogic,s905x",
17 "amlogic,meson-gxl";
18 model = "Libre Computer AML-S905X-CC";
25 dio2133: analog-amplifier {
26 compatible = "simple-audio-amplifier";
[all …]
H A Dmeson-gxl-s805x-libretech-ac.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/sound/meson-aiu.h>
13 #include "meson-gxl-s805x.dtsi"
16 compatible = "libretech,aml-s805x-ac", "amlogic,s805x",
17 "amlogic,meson-gxl";
18 model = "Libre Computer AML-S805X-AC";
27 stdout-path = "serial0:115200n8";
30 cvbs-connector {
[all …]
H A Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/sound/meson-aiu.h>
13 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
22 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
33 led-stat {
34 label = "nanopi-k2:blue:stat";
[all …]
H A Dmeson-gxl-s905x-khadas-vim.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxl-s905x-p212.dtsi"
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/sound/meson-aiu.h>
13 compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl";
16 adc-keys {
17 compatible = "adc-keys";
18 io-channels = <&saradc 0>;
19 io-channel-names = "buttons";
[all …]
H A Dmeson-gxbb-odroidc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/sound/meson-aiu.h>
15 compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
16 model = "Hardkernel ODROID-C2";
24 stdout-path = "serial0:115200n8";
32 usb_otg_pwr: regulator-usb-pwrs {
33 compatible = "regulator-fixed";
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dmeson-gxl-s905x-khadas-vim.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
10 #include "meson-gxl-s905x-p212.dtsi"
13 compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl";
16 adc-keys {
17 compatible = "adc-keys";
18 io-channels = <&saradc 0>;
19 io-channel-names = "buttons";
20 keyup-threshold-microvolt = <1710000>;
[all …]
H A Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
12 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
20 stdout-path = "serial0:115200n8";
29 compatible = "gpio-leds";
32 label = "nanopi-k2:blue:stat";
34 default-state = "on";
35 panic-indicator;
[all …]
H A Dmeson-gxbb-odroidc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
14 compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
15 model = "Hardkernel ODROID-C2";
23 stdout-path = "serial0:115200n8";
31 usb_otg_pwr: regulator-usb-pwrs {
32 compatible = "regulator-fixed";
34 regulator-name = "USB_OTG_PWR";
[all …]
H A Dmeson-gxl-s905x-libretech-cc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
12 #include "meson-gxl-s905x.dtsi"
15 compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
16 model = "Libre Computer Board AML-S905X-CC";
24 stdout-path = "serial0:115200n8";
27 cvbs-connector {
28 compatible = "composite-video-connector";
32 remote-endpoint = <&cvbs_vdac_out>;
[all …]
/openbmc/u-boot/board/bticino/mamoj/
H A DREADME10 This will generate the SPL image called SPL and the u-boot-dtb.img.
14 1. USB SDP boot
16 2. eMMC boot (via DFU)
20 1. USB SDP boot:
21 ---------------
23 - Build imx_usb_loader
29 - Build the BSP and copy SPL, u-boot-dtb.img in imx_usb_loader directory
31 - Put the board in "Serial Download Mode"
33 - Plug-in USB-to-Serial, Open minicom 1152008N1 and USB OTG cables to Host
35 - Turn-on board
[all …]
/openbmc/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8b-ec100.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
22 stdout-path = "serial0:115200n8";
30 emmc_pwrseq: emmc-pwrseq {
31 compatible = "mmc-pwrseq-emmc";
32 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
35 gpio-keys {
36 compatible = "gpio-keys-polled";
[all …]
H A Dmeson8b-odroidc1.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
12 model = "Hardkernel ODROID-C1";
13 compatible = "hardkernel,odroid-c1", "amlogic,meson8b";
22 stdout-path = "serial0:115200n8";
30 emmc_pwrseq: emmc-pwrseq {
31 compatible = "mmc-pwrseq-emmc";
32 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
36 compatible = "gpio-leds";
[all …]
/openbmc/qemu/hw/sd/
H A Dallwinner-sdhost.c27 #include "hw/qdev-properties.h"
29 #include "hw/sd/allwinner-sdhost.h"
34 #define TYPE_AW_SDHOST_BUS "allwinner-sdhost-bus"
69 REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */
70 REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */
71 REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */
72 REG_SD_DATA6_CRC = 0x118, /* CRC Data 6 from card/eMMC */
73 REG_SD_DATA5_CRC = 0x11C, /* CRC Data 5 from card/eMMC */
74 REG_SD_DATA4_CRC = 0x120, /* CRC Data 4 from card/eMMC */
75 REG_SD_DATA3_CRC = 0x124, /* CRC Data 3 from card/eMMC */
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/boot-device/
H A Dboot-device-ld11.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016-2017 Socionext Inc.
12 #include "boot-device.h"
23 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
24 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
25 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
26 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
27 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
28 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
29 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3368-evb.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2015 Caesar Wang <wxt@rock-chips.com>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/pwm/pwm.h>
12 mmc0 = &emmc;
16 stdout-path = "serial2:115200n8";
25 compatible = "pwm-backlight";
26 brightness-levels = <
27 0 1 2 3 4 5 6 7
59 default-brightness-level = <128>;
[all …]
/openbmc/qemu/include/hw/misc/
H A Dxlnx-versal-pmc-iou-slcr.h28 * module documented in Versal's Technical Reference manual [1] and the Versal
33 * [1] Versal ACAP Technical Reference Manual,
34 * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
37 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/PMC_IOP_SLCR-Module
43 * + sysbus IRQ 1: Device interrupt.
44 * + Named GPIO output "sd-emmc-sel[0]": Enables 0: SD mode or 1: eMMC mode on
45 * SD/eMMC controller 0.
46 * + Named GPIO output "sd-emmc-sel[1]": Enables 0: SD mode or 1: eMMC mode on
47 * SD/eMMC controller 1.
48 * + Named GPIO output "qspi-ospi-mux-sel": Selects 0: QSPI linear region or 1:
[all …]
/openbmc/docs/architecture/code-update/
H A Demmc-storage-design.md1 # eMMC Storage Design
7 Created: 2019-06-20
11 Proposal to define an initial storage design for an eMMC device. This includes
22 - Security: Ability to enforce read-only, verification of official/signed images
25 - Updatable: Ensure that the filesystem design allows for an effective and
28 - Simplicity: Make the system easy to understand, so that it is easy to develop,
31 - Code reuse: Try to use something that already exists instead of re-inventing
36 - The eMMC image layout and characteristics are specified in a meta layer. This
41 - Code update: Support two versions on flash. This allows a known good image to
44 - GPT partitioning for the eMMC User Data Area: This is chosen over dynamic
[all …]
/openbmc/u-boot/board/freescale/mx6sabresd/
H A DREADME1 How to use and build U-Boot on mx6sabresd
2 -----------------------------------------
6 1. Booting from SD card
8 2. Booting from eMMC
13 1. Booting from SD card via SPL
14 -------------------------------
24 This will generate the SPL and u-boot-dtb.img binaries.
26 - Flash the SPL binary into the SD card:
28 $ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
30 - Flash the u-boot-dtb.img binary into the SD card:
[all …]
/openbmc/openbmc/meta-aspeed/recipes-bsp/u-boot/files/
H A DevbA3_emmc_patch.json22 // OTPCFG14[10-0]
24 // OTPCFG14[16-11] 24 DW
28 // OTPSTRAP[1]
29 "Enable boot from eMMC": {
30 // false: Disable boot from eMMC
31 // true : Enable boot from eMMC
37 "Enable boot SPI or eMMC ABR": {
38 // false: Disable boot SPI or eMMC ABR
39 // true : Enable boot SPI or eMMC ABR
/openbmc/qemu/docs/system/arm/
H A Daspeed.rst1 …-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280…
6 Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the
8 with dual cores ARM Cortex-A7 CPUs (1.2GHz) and more recently the AST2700
9 with quad cores ARM Cortex-A35 64 bits CPUs (1.6GHz)
16 - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
17 - ``quanta-q71l-bmc`` OpenBMC Quanta BMC
18 - ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S)
19 - ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176)
23 - ``ast2500-evb`` Aspeed AST2500 Evaluation board
24 - ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC
[all …]

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