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/openbmc/linux/arch/sh/include/asm/
H A Dbl_bit_32.h10 "stc sr, %0\n\t" in set_bl_bit()
11 "or %2, %0\n\t" in set_bl_bit()
12 "and %3, %0\n\t" in set_bl_bit()
13 "ldc %0, sr\n\t" in set_bl_bit()
15 : "r" (0x10000000), "r" (0xffffff0f) in set_bl_bit()
25 "stc sr, %0\n\t" in clear_bl_bit()
26 "and %2, %0\n\t" in clear_bl_bit()
27 "ldc %0, sr\n\t" in clear_bl_bit()
29 : "1" (~0x10000000) in clear_bl_bit()
/openbmc/u-boot/arch/sh/include/asm/
H A Dirqflags.h9 "stc sr, %0\n\t" in raw_local_irq_enable()
10 "and %1, %0\n\t" in raw_local_irq_enable()
13 "or %1, %0\n\t" in raw_local_irq_enable()
15 "ldc %0, sr\n\t" in raw_local_irq_enable()
17 : "1" (~0x000000f0) in raw_local_irq_enable()
27 "stc sr, %0\n\t" in raw_local_irq_disable()
28 "or #0xf0, %0\n\t" in raw_local_irq_disable()
29 "ldc %0, sr\n\t" in raw_local_irq_disable()
41 "stc sr, %0\n\t" in set_bl_bit()
42 "or %2, %0\n\t" in set_bl_bit()
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/openbmc/u-boot/arch/m68k/include/asm/coldfire/
H A Dssi.h23 u8 resv0[0x4];
25 u8 resv1[0x8];
34 #define SSI_CR_CIS (0x00000200)
35 #define SSI_CR_TCH (0x00000100)
36 #define SSI_CR_MCE (0x00000080)
37 #define SSI_CR_I2S_MASK (0xFFFFFF9F)
38 #define SSI_CR_I2S_SLAVE (0x00000040)
39 #define SSI_CR_I2S_MASTER (0x00000020)
40 #define SSI_CR_I2S_NORMAL (0x00000000)
41 #define SSI_CR_SYN (0x00000010)
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/openbmc/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
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/openbmc/linux/drivers/gpu/drm/radeon/
H A Drs690d.h32 #define R_00001E_K8_FB_LOCATION 0x00001E
33 #define R_00005F_MC_MISC_UMA_CNTL 0x00005F
34 #define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF)
35 #define R_000078_MC_INDEX 0x000078
36 #define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0)
37 #define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF)
38 #define C_000078_MC_IND_ADDR 0xFFFFFE00
39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9)
40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1)
41 #define C_000078_MC_IND_WR_EN 0xFFFFFDFF
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H A Dr600d.h30 #define CP_PACKET2 0x80000000
31 #define PACKET2_PAD_SHIFT 0
32 #define PACKET2_PAD_MASK (0x3fffffff << 0)
41 #define R6XX_MAX_BACKENDS_MASK 0xff
43 #define R6XX_MAX_SIMDS_MASK 0xff
45 #define R6XX_MAX_PIPES_MASK 0xff
48 #define ARRAY_LINEAR_GENERAL 0x00000000
49 #define ARRAY_LINEAR_ALIGNED 0x00000001
50 #define ARRAY_1D_TILED_THIN1 0x00000002
51 #define ARRAY_2D_TILED_THIN1 0x00000004
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H A Devergreend.h33 #define EVERGREEN_MAX_BACKENDS_MASK 0xFF
35 #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
37 #define EVERGREEN_MAX_PIPES_MASK 0xFF
38 #define EVERGREEN_MAX_LDS_NUM 0xFFFF
40 #define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003
41 #define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003
42 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
43 #define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002
44 #define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002
45 #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002
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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp.h9 #define MV_78XX0_Z1_REV 0x0
10 #define MV_78XX0_A0_REV 0x1
11 #define MV_78XX0_B0_REV 0x2
13 #define SAR_DDR3_FREQ_MASK 0xFE00000
14 #define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24))
18 #define MIN_DIMM_ADDR 0x50
19 #define FAR_END_DIMM_ADDR 0x50
20 #define MAX_DIMM_ADDR 0x60
23 #define SDRAM_CS_SIZE 0xFFFFFFF
27 #define SDRAM_CS_BASE 0x0
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/openbmc/linux/drivers/platform/x86/
H A Dlg-laptop.c43 #define GOV_TLED 0x2020008
46 #define WM_KEY_LIGHT 0x400
47 #define WM_TLED 0x404
48 #define WM_FN_LOCK 0x407
49 #define WM_BATT_LIMIT 0x61
50 #define WM_READER_MODE 0xBF
51 #define WM_FAN_MODE 0x33
52 #define WMBB_USB_CHARGE 0x10B
53 #define WMBB_BATT_LIMIT 0x10C
68 #define INIT_INPUT_WMI_0 0x01
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/openbmc/u-boot/board/xilinx/zynqmp/zynqmp-zc1232-revA/
H A Dpsu_init_gpl.c11 psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); in psu_pll_init_data()
12 psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); in psu_pll_init_data()
13 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); in psu_pll_init_data()
14 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); in psu_pll_init_data()
15 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); in psu_pll_init_data()
16 mask_poll(0xFF5E0040, 0x00000002U); in psu_pll_init_data()
17 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); in psu_pll_init_data()
18 psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); in psu_pll_init_data()
19 psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU); in psu_pll_init_data()
20 psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); in psu_pll_init_data()
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/openbmc/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/
H A Dpsu_init_gpl.c11 psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); in psu_pll_init_data()
12 psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U); in psu_pll_init_data()
13 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); in psu_pll_init_data()
14 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); in psu_pll_init_data()
15 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); in psu_pll_init_data()
16 mask_poll(0xFF5E0040, 0x00000002U); in psu_pll_init_data()
17 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); in psu_pll_init_data()
18 psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); in psu_pll_init_data()
19 psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U); in psu_pll_init_data()
20 psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); in psu_pll_init_data()
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/openbmc/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/
H A Dpsu_init_gpl.c11 psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); in psu_pll_init_data()
12 psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); in psu_pll_init_data()
13 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); in psu_pll_init_data()
14 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); in psu_pll_init_data()
15 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); in psu_pll_init_data()
16 mask_poll(0xFF5E0040, 0x00000002U); in psu_pll_init_data()
17 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); in psu_pll_init_data()
18 psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); in psu_pll_init_data()
19 psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU); in psu_pll_init_data()
20 psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); in psu_pll_init_data()
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/openbmc/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/
H A Dpsu_init_gpl.c11 psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); in psu_pll_init_data()
12 psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); in psu_pll_init_data()
13 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); in psu_pll_init_data()
14 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); in psu_pll_init_data()
15 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); in psu_pll_init_data()
16 mask_poll(0xFF5E0040, 0x00000002U); in psu_pll_init_data()
17 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); in psu_pll_init_data()
18 psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); in psu_pll_init_data()
19 psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU); in psu_pll_init_data()
20 psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); in psu_pll_init_data()
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/openbmc/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/
H A Dpsu_init_gpl.c11 psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); in psu_pll_init_data()
12 psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); in psu_pll_init_data()
13 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); in psu_pll_init_data()
14 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); in psu_pll_init_data()
15 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); in psu_pll_init_data()
16 mask_poll(0xFF5E0040, 0x00000002U); in psu_pll_init_data()
17 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); in psu_pll_init_data()
18 psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); in psu_pll_init_data()
19 psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU); in psu_pll_init_data()
20 psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); in psu_pll_init_data()
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/openbmc/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/
H A Dpsu_init_gpl.c11 psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); in psu_pll_init_data()
12 psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); in psu_pll_init_data()
13 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); in psu_pll_init_data()
14 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); in psu_pll_init_data()
15 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); in psu_pll_init_data()
16 mask_poll(0xFF5E0040, 0x00000002U); in psu_pll_init_data()
17 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); in psu_pll_init_data()
18 psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); in psu_pll_init_data()
19 psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU); in psu_pll_init_data()
20 psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); in psu_pll_init_data()
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/openbmc/u-boot/board/xilinx/zynqmp/zynqmp-zcu104-revA/
H A Dpsu_init_gpl.c11 psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); in psu_pll_init_data()
12 psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); in psu_pll_init_data()
13 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); in psu_pll_init_data()
14 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); in psu_pll_init_data()
15 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); in psu_pll_init_data()
16 mask_poll(0xFF5E0040, 0x00000002U); in psu_pll_init_data()
17 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); in psu_pll_init_data()
18 psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); in psu_pll_init_data()
19 psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U); in psu_pll_init_data()
20 psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); in psu_pll_init_data()
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/openbmc/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/
H A Dpsu_init_gpl.c11 psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U); in psu_pll_init_data()
12 psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015900U); in psu_pll_init_data()
13 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); in psu_pll_init_data()
14 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); in psu_pll_init_data()
15 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); in psu_pll_init_data()
16 mask_poll(0xFF5E0040, 0x00000002U); in psu_pll_init_data()
17 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); in psu_pll_init_data()
18 psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); in psu_pll_init_data()
19 psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x80008E69U); in psu_pll_init_data()
20 psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U); in psu_pll_init_data()
[all …]
/openbmc/u-boot/board/xilinx/zynqmp/zynqmp-zcu100-revC/
H A Dpsu_init_gpl.c11 psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); in psu_pll_init_data()
12 psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); in psu_pll_init_data()
13 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); in psu_pll_init_data()
14 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); in psu_pll_init_data()
15 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); in psu_pll_init_data()
16 mask_poll(0xFF5E0040, 0x00000002U); in psu_pll_init_data()
17 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); in psu_pll_init_data()
18 psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); in psu_pll_init_data()
19 psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U); in psu_pll_init_data()
20 psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); in psu_pll_init_data()
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/openbmc/linux/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic_init.c23 #define NETXEN_ADDR_ERROR (0xffffffff)
29 #define NETXEN_NIC_XDMA_RESET 0x8000ff
99 for (ring = 0; ring < adapter->max_rds_rings; ring++) { in netxen_release_rx_buffers()
101 for (i = 0; i < rds_ring->num_desc; ++i) { in netxen_release_rx_buffers()
122 for (i = 0; i < tx_ring->num_desc; i++) { in netxen_release_tx_buffers()
127 buffrag->dma = 0ULL; in netxen_release_tx_buffers()
135 buffrag->dma = 0ULL; in netxen_release_tx_buffers()
159 for (ring = 0; ring < adapter->max_rds_rings; ring++) { in netxen_free_sw_resources()
195 tx_ring->txq = netdev_get_tx_queue(netdev, 0); in netxen_alloc_sw_resources()
212 for (ring = 0; ring < adapter->max_rds_rings; ring++) { in netxen_alloc_sw_resources()
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/openbmc/u-boot/arch/arm/mach-aspeed/ast2500/
H A Dplatform.S34 * V2 |2014.10.31 : 1.[P2] Enable VGA wide screen support (SCU40[0]=1)
63 * |2016.07.12 : 2.[P1] Modify DDR4 read path ODT from 60 ohm to 48 ohm, at address 0x1e6e0204
64 … | : 3.[P1] Modify DDR4 Ron calibration to manual mode to fix Vix issue, set Ron_pu = 0
120 #define ASTMMC_INIT_VER 0x12 @ 8bit verison number
121 #define ASTMMC_INIT_DATE 0x20171027 @ Release date
133 //#define ASTMMC_DDR4_MANUAL_RPU 0x0 @ 0x0-0xF, larger value means weaker driving
134 //#define ASTMMC_DDR4_MANUAL_RPD 0x0 @ 0x0-0xF, larger value means stronger driving
157 #define ASTMMC_REGIDX_010 0x00
158 #define ASTMMC_REGIDX_014 0x04
159 #define ASTMMC_REGIDX_018 0x08
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