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Searched +full:0 +full:xfffff0 (Results 1 – 19 of 19) sorted by relevance

/openbmc/u-boot/drivers/net/phy/
H A Dmicrel_ksz8xxx.c18 .uid = 0x221510,
19 .mask = 0xfffff0,
26 #define MII_KSZPHY_OMSO 0x16
34 if (ret < 0) in ksz_genconfig_bcastoff()
39 if (ret < 0) in ksz_genconfig_bcastoff()
47 .uid = 0x221550,
48 .mask = 0xfffff0,
58 #define MII_KSZ8051_PHY_OMSO 0x16
75 .uid = 0x221550,
76 .mask = 0xfffff0,
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H A Dbroadcom.c12 #define MIIM_BCM54xx_AUXCNTL 0x18
13 #define MIIM_BCM54xx_AUXCNTL_ENCODE(val) (((val & 0x7) << 12)|(val & 0x7))
14 #define MIIM_BCM54xx_AUXSTATUS 0x19
15 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700
18 #define MIIM_BCM54XX_SHD 0x1c
19 #define MIIM_BCM54XX_SHD_WRITE 0x8000
20 #define MIIM_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
21 #define MIIM_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
26 #define MIIM_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
27 #define MIIM_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
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H A Dlxt.c12 #define MIIM_LXT971_SR2 0x11 /* Status Register 2 */
13 #define MIIM_LXT971_SR2_SPEED_MASK 0x4200
14 #define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */
15 #define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */
16 #define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
17 #define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */
47 return 0; in lxt971_parse_status()
63 .uid = 0x1378e0,
64 .mask = 0xfffff0,
75 return 0; in phy_lxt_init()
H A Dmicrel_ksz90x1.c21 #define MII_KSZ90xx_PHY_CTL 0x1f
28 #define MII_KSZ9021_EXTENDED_CTRL 0x0b
29 #define MII_KSZ9021_EXTENDED_DATAW 0x0c
30 #define MII_KSZ9021_EXTENDED_DATAR 0x0d
37 #define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
38 #define MII_KSZ9031_MMD_REG_DATA 0x0e
62 return 0; in ksz90xx_startup()
70 const u8 off; /* Offset from bit 0 */
82 { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
83 { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
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H A Drealtek.c23 #define MIIM_RTL8211x_PHY_STATUS 0x11
24 #define MIIM_RTL8211x_PHYSTAT_SPEED 0xc000
25 #define MIIM_RTL8211x_PHYSTAT_GBIT 0x8000
26 #define MIIM_RTL8211x_PHYSTAT_100 0x4000
27 #define MIIM_RTL8211x_PHYSTAT_DUPLEX 0x2000
28 #define MIIM_RTL8211x_PHYSTAT_SPDDONE 0x0800
29 #define MIIM_RTL8211x_PHYSTAT_LINK 0x0400
32 #define MIIM_RTL8211x_PHY_INER 0x12
33 #define MIIM_RTL8211x_PHY_INTR_ENA 0x9f01
34 #define MIIM_RTL8211x_PHY_INTR_DIS 0x0000
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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Drenesas,tpu.yaml53 reg = <0xffffe0 16>, <0xfffff0 12>;
/openbmc/linux/drivers/media/tuners/
H A Dmc44s803_priv.h14 SPI or I2C Address : 0xc0-0xc6
28 0A | LNA AGC
29 0B | Data Register Address
30 0C | Regulator Test
31 0D | VCO Test
32 0E | LNA Gain/Input Power
33 0F | ID Bits
41 #define MC44S803_REG_POWER 0
51 #define MC44S803_REG_LNAAGC 0x0A
52 #define MC44S803_REG_DATAREG 0x0B
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/openbmc/linux/drivers/soc/qcom/
H A Dllcc-qcom.c21 #define ACTIVATE BIT(0)
23 #define ACT_CLEAR BIT(0)
25 #define ACT_CTRL_OPCODE_ACTIVATE BIT(0)
27 #define ACT_CTRL_ACT_TRIG BIT(0)
28 #define ACT_CTRL_OPCODE_SHIFT 0x01
29 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02
30 #define ATTR1_FIXED_SIZE_SHIFT 0x03
31 #define ATTR1_PRIORITY_SHIFT 0x04
32 #define ATTR1_MAX_CAP_SHIFT 0x10
33 #define ATTR0_RES_WAYS_MASK GENMASK(15, 0)
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/openbmc/linux/drivers/crypto/ccree/
H A Dcc_aead.c78 ctx->enckey_dma_addr = 0; in cc_aead_exit()
92 xcbc->xcbc_keys_dma_addr = 0; in cc_aead_exit()
103 hmac->ipad_opad_dma_addr = 0; in cc_aead_exit()
112 hmac->padded_authkey_dma_addr = 0; in cc_aead_exit()
201 return 0; in cc_aead_init()
229 ctx->authsize) != 0) { in cc_aead_complete()
255 hw_desc_init(&desc[0]); in xcbc_setkey()
260 set_din_type(&desc[0], DMA_DLLI, in xcbc_setkey()
263 set_cipher_mode(&desc[0], DRV_CIPHER_ECB); in xcbc_setkey()
264 set_cipher_config0(&desc[0], DRV_CRYPTO_DIRECTION_ENCRYPT); in xcbc_setkey()
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H A Dcc_hash.c29 0x00000040, 0x00000000, 0x00000000, 0x00000000 };
41 0x00000080, 0x00000000, 0x00000000, 0x00000000 };
132 return 0; in cc_map_result()
140 memset(state, 0, sizeof(*state)); in cc_init_req()
225 return 0; in cc_map_req()
231 state->digest_bytes_len_dma_addr = 0; in cc_map_req()
237 state->digest_buff_dma_addr = 0; in cc_map_req()
251 state->digest_buff_dma_addr = 0; in cc_unmap_req()
258 state->digest_bytes_len_dma_addr = 0; in cc_unmap_req()
265 state->opad_digest_dma_addr = 0; in cc_unmap_req()
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/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2.h28 #define MVPP2_XDP_PASS 0
29 #define MVPP2_XDP_DROPPED BIT(0)
34 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
35 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
36 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
37 #define MVPP2_RX_FIFO_INIT_REG 0x64
38 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port))
39 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port))
42 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
43 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
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/openbmc/linux/drivers/misc/sgi-gru/
H A Dgrutables.h54 * | context 0 |
268 } while (0)
275 } while (0)
283 #define MAX_ASID 0xfffff0
368 signed char ts_blade; /* If >= 0, migrate context if
510 for ((gru) = gru_base[nid]->bs_grus, (i) = 0; \
516 for ((gid) = 0; (gid) < gru_max_gids; (gid)++)
520 for ((ctxnum) = 0; (ctxnum) < GRU_NUM_CCH; (ctxnum)++) \
545 /* 0 = lock failed, 1 = locked */
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
H A Dbif_5_0_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
H A Dbif_5_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A DMC68328.h26 * 0xFFFFF0xx -- System Control
33 #define SCR_ADDR 0xfffff000
36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
37 #define SCR_DMAP 0x04 /* Double Map */
38 #define SCR_SO 0x08 /* Supervisor Only */
39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
40 #define SCR_PRV 0x20 /* Privilege Violation */
41 #define SCR_WPV 0x40 /* Write Protect Violation */
42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
47 #define MRR_ADDR 0xfffff004
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/openbmc/linux/drivers/scsi/bfa/
H A Dbfa_fc.h18 #define WWN_NULL (0)
36 #define SCSI_MAX_ALLOC_LEN 0xFF /* maximum allocarion length */
71 FC_RTG_FC4_DEV_DATA = 0x0, /* FC-4 Device Data */
72 FC_RTG_EXT_LINK = 0x2, /* Extended Link Data */
73 FC_RTG_FC4_LINK_DATA = 0x3, /* FC-4 Link Data */
74 FC_RTG_VIDEO_DATA = 0x4, /* Video Data */
75 FC_RTG_EXT_HDR = 0x5, /* VFT, IFR or Encapsuled */
76 FC_RTG_BASIC_LINK = 0x8, /* Basic Link data */
77 FC_RTG_LINK_CTRL = 0xC, /* Link Control */
84 FC_CAT_LD_REQUEST = 0x2, /* Request */
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/openbmc/linux/sound/isa/sb/
H A Demu8000.c99 unsigned right_bit = (mode & EMU8000_RAM_RIGHT) ? 0x01000000 : 0; in snd_emu8000_dma_chan()
102 EMU8000_CCCA_WRITE(emu, ch, 0); in snd_emu8000_dma_chan()
103 EMU8000_DCYSUSV_WRITE(emu, ch, 0x807F); in snd_emu8000_dma_chan()
106 EMU8000_DCYSUSV_WRITE(emu, ch, 0x80); in snd_emu8000_dma_chan()
107 EMU8000_VTFT_WRITE(emu, ch, 0); in snd_emu8000_dma_chan()
108 EMU8000_CVCF_WRITE(emu, ch, 0); in snd_emu8000_dma_chan()
109 EMU8000_PTRX_WRITE(emu, ch, 0x40000000); in snd_emu8000_dma_chan()
110 EMU8000_CPF_WRITE(emu, ch, 0x40000000); in snd_emu8000_dma_chan()
111 EMU8000_PSST_WRITE(emu, ch, 0); in snd_emu8000_dma_chan()
112 EMU8000_CSL_WRITE(emu, ch, 0); in snd_emu8000_dma_chan()
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/openbmc/linux/drivers/scsi/
H A Dscsi_transport_fc.c76 for (i = 0; i < ARRAY_SIZE(table); i++) { \
91 for (i = 0; i < ARRAY_SIZE(table); i++) { \
93 table[i].matchlen) == 0) { \
95 return 0; /* success */ \
218 ssize_t len = 0; \
221 for (i = 0; i < ARRAY_SIZE(table); i++) { \
275 int i, len=0; in fc_bitfield_name_search()
277 for (i = 0; i < FC_FC4_LIST_SIZE; i++, fc4_list++) in fc_bitfield_name_search()
278 len += sprintf(buf + len , "0x%02x ", *fc4_list); in fc_bitfield_name_search()
302 #define FC_WELLKNOWN_PORTID_MASK 0xfffff0
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