Searched +full:0 +full:xfff8c000 (Results 1 – 9 of 9) sorted by relevance
7 #define FIRMWARE_START 0xf00000008 #define FIRMWARE_END 0xf080000010 #define DEVICE_HPA_LEN 0x0010000012 #define GSC_HPA 0xffc0000013 #define DINO_HPA 0xfff8000014 #define DINO_UART_HPA 0xfff8300015 #define DINO_UART_BASE 0xfff8380016 #define DINO_SCSI_HPA 0xfff8c00017 #define LASI_HPA 0xffd0000018 #define LASI_UART_HPA 0xffd05000[all …]
19 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */26 #define ATMEL_ID_USART0 7 /* USART 0 */29 #define ATMEL_ID_MCI0 10 /* Multimedia Card Interface 0 */33 #define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */35 #define ATMEL_ID_SSC0 16 /* Serial Synchronous Controller 0 */38 #define ATMEL_ID_TCB 19 /* Timer Counter 0, 1 and 2 */55 #define ATMEL_BASE_UDP 0xfff7800056 #define ATMEL_BASE_TCB0 0xfff7c00057 #define ATMEL_BASE_TC0 0xfff7c00058 #define ATMEL_BASE_TC1 0xfff7c040[all …]
17 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */24 #define ATMEL_ID_USART0 7 /* USART 0 */28 #define ATMEL_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */29 #define ATMEL_ID_TWI0 12 /* Two-Wire Interface 0 */31 #define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */33 #define ATMEL_ID_SSC0 16 /* Synchronous Serial Controller 0 */35 #define ATMEL_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */53 #define ATMEL_BASE_UDPHS 0xfff7800054 #define ATMEL_BASE_TC0 0xfff7c00055 #define ATMEL_BASE_TC1 0xfff7c040[all …]
67 enum: [ 0, 1 ]109 const: 0135 reg = <0xfff8c000 0x4000>;159 reg = <0xf001c000 0x100>;181 reg = <0xf001c000 0x100>;183 #size-cells = <0>;
40 #size-cells = <0>;42 cpu@0 {45 reg = <0>;51 reg = <0x20000000 0x08000000>;57 #clock-cells = <0>;58 clock-frequency = <0>;63 #clock-cells = <0>;64 clock-frequency = <0>;70 reg = <0x00300000 0x14000>;73 ranges = <0 0x00300000 0x14000>;[all …]
46 #size-cells = <0>;48 cpu@0 {51 reg = <0>;57 reg = <0x70000000 0x10000000>;63 #clock-cells = <0>;64 clock-frequency = <0>;69 #clock-cells = <0>;70 clock-frequency = <0>;75 #clock-cells = <0>;82 reg = <0x00300000 0x10000>;[all …]
13 #define BCM3368_CPU_ID 0x336814 #define BCM6328_CPU_ID 0x632815 #define BCM6338_CPU_ID 0x633816 #define BCM6345_CPU_ID 0x634517 #define BCM6348_CPU_ID 0x634818 #define BCM6358_CPU_ID 0x635819 #define BCM6362_CPU_ID 0x636220 #define BCM6368_CPU_ID 0x636891 RSET_DSL_LMEM = 0,166 #define BCM_3368_DSL_LMEM_BASE (0xdeadbeef)[all …]
46 reg = <0x20000000 0x08000000>;52 #clock-cells = <0>;53 clock-frequency = <0>;58 #clock-cells = <0>;59 clock-frequency = <0>;65 reg = <0x00300000 0x14000>;70 reg = <0x00500000 0x4000>;91 reg = <0xfffff000 0x200>;97 reg = <0xfffffc00 0x100>;101 #size-cells = <0>;[all …]
51 reg = <0x70000000 0x10000000>;57 #clock-cells = <0>;58 clock-frequency = <0>;63 #clock-cells = <0>;64 clock-frequency = <0>;69 #clock-cells = <0>;76 reg = <0x00300000 0x10000>;97 reg = <0xfffff000 0x200>;103 reg = <0xffffe400 0x200>;110 reg = <0xffffe600 0x200>;[all …]