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Searched +full:0 +full:xffe08000 (Results 1 – 19 of 19) sorted by relevance

/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh7763.h11 #define CCR 0xFF00001C
12 #define CCR_CACHE_INIT 0x0000090b
17 #define SCSMR0 0xFFE00000
21 #define SCSMR1 0xFFE08000
25 #define SCSMR2 0xFFE10000
29 #define WDTST 0xFFCC0000
32 #define TMU_BASE 0xFFD80000
/openbmc/u-boot/board/highbank/
H A Dahci.c10 #define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
11 #define CPHY_ADDR(base, dev, addr) ((base) | (((addr) & 0x1ff) << 2))
12 #define CPHY_BASE 0xfff58000
13 #define CPHY_WIDTH 0x1000
16 #define SERDES_CR_CTL 0x80a0
17 #define SERDES_CR_ADDR 0x80a1
18 #define SERDES_CR_DATA 0x80a2
19 #define CR_BUSY 0x0001
20 #define CR_START 0x0001
21 #define CR_WR_RDN 0x0002
[all …]
H A Dhighbank.c14 #define HB_AHCI_BASE 0xffe08000
16 #define HB_SCU_A9_PWR_STATUS 0xfff10008
17 #define HB_SREG_A9_PWR_REQ 0xfff3cf00
18 #define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04
19 #define HB_SREG_A9_PWRDOM_STAT 0xfff3cf20
20 #define HB_SREG_A15_PWR_CTRL 0xfff3c200
22 #define HB_PWR_SUSPEND 0
27 #define PWRDOM_STAT_SATA 0x80000000
28 #define PWRDOM_STAT_PCI 0x40000000
29 #define PWRDOM_STAT_EMMC 0x20000000
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dp2020ds.dts19 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
20 0x1 0x0 0x0 0xe0000000 0x08000000
21 0x2 0x0 0x0 0xffa00000 0x00040000
22 0x3 0x0 0x0 0xffdf0000 0x00008000
23 0x4 0x0 0x0 0xffa40000 0x00040000
24 0x5 0x0 0x0 0xffa80000 0x00040000
25 0x6 0x0 0x0 0xffac0000 0x00040000>;
26 reg = <0 0xffe05000 0 0x1000>;
30 ranges = <0x0 0x0 0xffe00000 0x100000>;
34 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
[all …]
H A Dmpc8572ds.dts19 reg = <0 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
22 0x1 0x0 0x0 0xe0000000 0x08000000
23 0x2 0x0 0x0 0xffa00000 0x00040000
24 0x3 0x0 0x0 0xffdf0000 0x00008000
25 0x4 0x0 0x0 0xffa40000 0x00040000
26 0x5 0x0 0x0 0xffa80000 0x00040000
27 0x6 0x0 0x0 0xffac0000 0x00040000>;
31 ranges = <0x0 0 0xffe00000 0x100000>;
35 reg = <0 0xffe08000 0 0x1000>;
[all …]
H A Dmpc8572ds_36b.dts19 reg = <0xf 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
22 0x1 0x0 0xf 0xe0000000 0x08000000
23 0x2 0x0 0xf 0xffa00000 0x00040000
24 0x3 0x0 0xf 0xffdf0000 0x00008000
25 0x4 0x0 0xf 0xffa40000 0x00040000
26 0x5 0x0 0xf 0xffa80000 0x00040000
27 0x6 0x0 0xf 0xffac0000 0x00040000>;
31 ranges = <0x0 0xf 0xffe00000 0x100000>;
35 reg = <0xf 0xffe08000 0 0x1000>;
[all …]
H A Dmpc8536ds_36b.dts17 #size-cells = <0>;
19 PowerPC,8536@0 {
21 reg = <0>;
28 reg = <0 0 0 0>; // Filled by U-Boot
32 reg = <0xf 0xffe05000 0 0x1000>;
34 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
35 0x2 0x0 0xf 0xffa00000 0x00040000
36 0x3 0x0 0xf 0xffdf0000 0x00008000>;
40 ranges = <0x0 0xf 0xffe00000 0x100000>;
44 reg = <0xf 0xffe08000 0 0x1000>;
[all …]
H A Dmpc8536ds.dts17 #size-cells = <0>;
19 PowerPC,8536@0 {
21 reg = <0>;
28 reg = <0 0 0 0>; // Filled by U-Boot
32 reg = <0 0xffe05000 0 0x1000>;
34 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
35 0x2 0x0 0x0 0xffa00000 0x00040000
36 0x3 0x0 0x0 0xffdf0000 0x00008000>;
40 ranges = <0x0 0 0xffe00000 0x100000>;
44 reg = <0 0xffe08000 0 0x1000>;
[all …]
H A Dp2020rdb-pc_32b.dts46 reg = <0 0xffe05000 0 0x1000>;
49 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
50 0x1 0x0 0x0 0xff800000 0x00040000
51 0x2 0x0 0x0 0xffb00000 0x00020000
52 0x3 0x0 0x0 0xffa00000 0x00020000>;
56 ranges = <0x0 0x0 0xffe00000 0x100000>;
60 reg = <0 0xffe08000 0 0x1000>;
65 reg = <0 0xffe09000 0 0x1000>;
66 ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
67 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
[all …]
H A Dp2020rdb-pc_36b.dts46 reg = <0xf 0xffe05000 0 0x1000>;
49 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
50 0x1 0x0 0xf 0xff800000 0x00040000
51 0x2 0x0 0xf 0xffb00000 0x00020000
52 0x3 0x0 0xf 0xffa00000 0x00020000>;
56 ranges = <0x0 0xf 0xffe00000 0x100000>;
60 reg = <0xf 0xffe08000 0 0x1000>;
65 reg = <0xf 0xffe09000 0 0x1000>;
66 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
67 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
[all …]
H A Dmvme2500.dts29 ranges = <0x0 0 0xffe00000 0x100000>;
34 reg = <0x4c>;
39 reg = <0x68>;
40 interrupts = <8 1 0 0>;
45 reg = <0x54>;
50 reg = <0x52>;
55 reg = <0x53>;
60 reg = <0x50>;
68 flash@0 {
70 reg = <0>;
[all …]
H A Dp2020rdb.dts29 reg = <0 0xffe05000 0 0x1000>;
32 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
33 0x1 0x0 0x0 0xffa00000 0x00040000
34 0x2 0x0 0x0 0xffb00000 0x00020000>;
36 nor@0,0 {
40 reg = <0x0 0x0 0x1000000>;
44 partition@0 {
47 reg = <0x0 0x00040000>;
54 reg = <0x00040000 0x00040000>;
61 reg = <0x00080000 0x00380000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/ata/
H A Dsata_highbank.yaml60 The upper 24 bits of each entry are always 0 and thus ignored.
83 reg = <0xffe08000 0x1000>;
86 calxeda,port-phys = <&combophy5 0>, <&combophy0 0>, <&combophy0 1>,
89 calxeda,led-order = <4 0 1 2 3>;
90 calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
92 calxeda,post-clocks = <0>;
H A Dahci-platform.yaml84 "^sata-port@[0-9a-f]+$":
141 reg = <0xffe08000 0x1000>;
151 reg = <0xf7e90000 0x1000>;
155 #size-cells = <0>;
159 sata0: sata-port@0 {
160 reg = <0>;
162 phys = <&sata_phy 0>;
/openbmc/linux/arch/arm/boot/dts/calxeda/
H A Decx-common.dtsi14 cpu_suspend = <0x84000002>;
15 cpu_off = <0x84000004>;
16 cpu_on = <0x84000006>;
27 reg = <0xffe08000 0x10000>;
28 interrupts = <0 83 4>;
30 calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
35 calxeda,led-order = <4 0 1 2 3>;
40 reg = <0xffe0e000 0x1000>;
41 interrupts = <0 90 4>;
48 reg = <0xfff20000 0x1000>;
[all …]
/openbmc/u-boot/drivers/serial/
H A Dserial_sh.c28 return sci_in(port, SCRFDR) & 0xff; in scif_rxfill()
33 if ((port->mapbase == 0xffe00000) || in scif_rxfill()
34 (port->mapbase == 0xffe08000)) { in scif_rxfill()
36 return sci_in(port, SCRFDR) & 0xff; in scif_rxfill()
61 sci_out(port, SCSMR, 0); in sh_serial_init_generic()
62 sci_out(port, SCSMR, 0); in sh_serial_init_generic()
65 sci_out(port, SCFCR, 0); in sh_serial_init_generic()
86 sci_out(port, SCLSR, 0x00); in handle_error()
98 return 0; in serial_raw_putc()
110 return 0; in sh_serial_tstc_generic()
[all …]
/openbmc/qemu/hw/arm/
H A Dhighbank.c41 #define SMP_BOOT_ADDR 0x100
42 #define SMP_BOOT_REG 0x40
43 #define MPCORE_PERIPHBASE 0xfff10000
45 #define MVBAR_ADDR 0x200
52 #define NUM_REGS 0x200
58 if (offset == 0xf00) { in hb_regs_write()
68 "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset); in hb_regs_write()
82 "highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset); in hb_regs_read()
83 return 0; in hb_regs_read()
87 if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) { in hb_regs_read()
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dturris1x.dts37 ranges = <0x0 0x0 0xffe00000 0x00100000>;
44 reg = <0x18>;
47 polarity = <0x00>;
57 reg = <0x2a>;
62 reg = <0x32>;
68 reg = <0x4c>;
73 #size-cells = <0>;
76 channel@0 {
77 reg = <0>;
91 reg = <0x52>;
[all …]
/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7763.c26 DEFINE_RES_MEM(0xffe00000, 0x100),
27 DEFINE_RES_IRQ(evt2irq(0x700)),
32 .id = 0,
47 DEFINE_RES_MEM(0xffe08000, 0x100),
48 DEFINE_RES_IRQ(evt2irq(0xb80)),
68 DEFINE_RES_MEM(0xffe10000, 0x100),
69 DEFINE_RES_IRQ(evt2irq(0xf00)),
83 [0] = {
84 .start = 0xffe80000,
85 .end = 0xffe80000 + 0x58 - 1,
[all …]