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/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dbase_addr_ac5.h9 #define SOCFPGA_FPGA_SLAVES_ADDRESS 0xc0000000
10 #define SOCFPGA_STM_ADDRESS 0xfc000000
11 #define SOCFPGA_DAP_ADDRESS 0xff000000
12 #define SOCFPGA_EMAC0_ADDRESS 0xff700000
13 #define SOCFPGA_EMAC1_ADDRESS 0xff702000
14 #define SOCFPGA_SDMMC_ADDRESS 0xff704000
15 #define SOCFPGA_QSPI_ADDRESS 0xff705000
16 #define SOCFPGA_GPIO0_ADDRESS 0xff708000
17 #define SOCFPGA_GPIO1_ADDRESS 0xff709000
18 #define SOCFPGA_GPIO2_ADDRESS 0xff70a000
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dp1020rdb.dts18 reg = <0 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
22 0x1 0x0 0x0 0xffa00000 0x00040000
23 0x2 0x0 0x0 0xffb00000 0x00020000>;
27 ranges = <0x0 0x0 0xffe00000 0x100000>;
31 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
32 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
33 reg = <0 0xffe09000 0 0x1000>;
34 pcie@0 {
35 ranges = <0x2000000 0x0 0xa0000000
[all …]
H A Dp1020rdb_36b.dts18 reg = <0xf 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
22 0x1 0x0 0xf 0xffa00000 0x00040000
23 0x2 0x0 0xf 0xffb00000 0x00020000>;
27 ranges = <0x0 0xf 0xffe00000 0x100000>;
31 reg = <0xf 0xffe09000 0 0x1000>;
32 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
33 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
34 pcie@0 {
35 ranges = <0x2000000 0x0 0xc0000000
[all …]
H A Dp1010rdb_32b.dtsi41 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
42 0x1 0x0 0x0 0xff800000 0x00010000
43 0x3 0x0 0x0 0xffb00000 0x00000020>;
44 reg = <0x0 0xffe1e000 0 0x2000>;
48 ranges = <0x0 0x0 0xffe00000 0x100000>;
52 reg = <0 0xffe09000 0 0x1000>;
53 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
54 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
55 pcie@0 {
56 ranges = <0x2000000 0x0 0xa0000000
[all …]
H A Dp1010rdb_36b.dtsi41 ranges = <0x0 0x0 0xf 0xee000000 0x02000000
42 0x1 0x0 0xf 0xff800000 0x00010000
43 0x3 0x0 0xf 0xffb00000 0x00000020>;
44 reg = <0xf 0xffe1e000 0 0x2000>;
48 ranges = <0x0 0xf 0xffe00000 0x100000>;
52 reg = <0xf 0xffe09000 0 0x1000>;
53 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
54 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
55 pcie@0 {
56 ranges = <0x2000000 0x0 0xc0000000
[all …]
H A Dp1021rdb-pc_36b.dts45 reg = <0xf 0xffe05000 0 0x1000>;
48 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
49 0x1 0x0 0xf 0xff800000 0x00040000
50 0x2 0x0 0xf 0xffb00000 0x00020000>;
54 ranges = <0x0 0xf 0xffe00000 0x100000>;
58 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
59 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
60 reg = <0xf 0xffe09000 0 0x1000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xa0000000
[all …]
H A Dp1021rdb-pc_32b.dts45 reg = <0 0xffe05000 0 0x1000>;
48 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
49 0x1 0x0 0x0 0xff800000 0x00040000
50 0x2 0x0 0x0 0xffb00000 0x00020000>;
54 ranges = <0x0 0x0 0xffe00000 0x100000>;
58 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
59 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
60 reg = <0 0xffe09000 0 0x1000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xa0000000
[all …]
H A Dp2020rdb-pc_32b.dts46 reg = <0 0xffe05000 0 0x1000>;
49 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
50 0x1 0x0 0x0 0xff800000 0x00040000
51 0x2 0x0 0x0 0xffb00000 0x00020000
52 0x3 0x0 0x0 0xffa00000 0x00020000>;
56 ranges = <0x0 0x0 0xffe00000 0x100000>;
60 reg = <0 0xffe08000 0 0x1000>;
65 reg = <0 0xffe09000 0 0x1000>;
66 ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
67 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
[all …]
H A Dp2020rdb-pc_36b.dts46 reg = <0xf 0xffe05000 0 0x1000>;
49 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
50 0x1 0x0 0xf 0xff800000 0x00040000
51 0x2 0x0 0xf 0xffb00000 0x00020000
52 0x3 0x0 0xf 0xffa00000 0x00020000>;
56 ranges = <0x0 0xf 0xffe00000 0x100000>;
60 reg = <0xf 0xffe08000 0 0x1000>;
65 reg = <0xf 0xffe09000 0 0x1000>;
66 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
67 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
[all …]
H A Dp1020rdb-pc_36b.dts45 reg = <0xf 0xffe05000 0 0x1000>;
48 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
49 0x1 0x0 0xf 0xff800000 0x00040000
50 0x2 0x0 0xf 0xffb00000 0x00040000
51 0x3 0x0 0xf 0xffa00000 0x00020000>;
55 ranges = <0x0 0xf 0xffe00000 0x100000>;
59 reg = <0xf 0xffe09000 0 0x1000>;
60 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
61 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
62 pcie@0 {
[all …]
H A Dp1020rdb-pc_32b.dts45 reg = <0 0xffe05000 0 0x1000>;
48 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
49 0x1 0x0 0x0 0xff800000 0x00040000
50 0x2 0x0 0x0 0xffb00000 0x00020000
51 0x3 0x0 0x0 0xffa00000 0x00020000>;
55 ranges = <0x0 0x0 0xffe00000 0x100000>;
59 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
61 reg = <0 0xffe09000 0 0x1000>;
62 pcie@0 {
[all …]
H A Dp1020utm-pc_36b.dts45 reg = <0xf 0xffe05000 0x0 0x1000>;
48 ranges = <0x0 0x0 0xf 0xec000000 0x02000000
49 0x1 0x0 0xf 0xffa00000 0x00040000
50 0x2 0x0 0xf 0xffb00000 0x00020000>;
54 ranges = <0x0 0xf 0xffe00000 0x100000>;
58 reg = <0xf 0xffe09000 0x0 0x1000>;
59 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xe0000000
[all …]
H A Dp1020mbg-pc_36b.dts45 reg = <0xf 0xffe05000 0x0 0x1000>;
48 ranges = <0x0 0x0 0xf 0xec000000 0x04000000
49 0x1 0x0 0xf 0xffa00000 0x00040000
50 0x2 0x0 0xf 0xffb00000 0x00020000>;
54 ranges = <0x0 0xf 0xffe00000 0x100000>;
58 reg = <0xf 0xffe09000 0x0 0x1000>;
59 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xe0000000
[all …]
H A Dp1020utm-pc_32b.dts45 reg = <0x0 0xffe05000 0x0 0x1000>;
48 ranges = <0x0 0x0 0x0 0xec000000 0x02000000
49 0x1 0x0 0x0 0xffa00000 0x00040000
50 0x2 0x0 0x0 0xffb00000 0x00020000>;
54 ranges = <0x0 0x0 0xffe00000 0x100000>;
58 reg = <0x0 0xffe09000 0x0 0x1000>;
59 ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xe0000000
[all …]
H A Dp1020mbg-pc_32b.dts45 reg = <0x0 0xffe05000 0x0 0x1000>;
48 ranges = <0x0 0x0 0x0 0xec000000 0x04000000
49 0x1 0x0 0x0 0xffa00000 0x00040000
50 0x2 0x0 0x0 0xffb00000 0x00020000>;
54 ranges = <0x0 0x0 0xffe00000 0x100000>;
58 reg = <0x0 0xffe09000 0x0 0x1000>;
59 ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xe0000000
[all …]
H A Dp2020rdb.dts29 reg = <0 0xffe05000 0 0x1000>;
32 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
33 0x1 0x0 0x0 0xffa00000 0x00040000
34 0x2 0x0 0x0 0xffb00000 0x00020000>;
36 nor@0,0 {
40 reg = <0x0 0x0 0x1000000>;
44 partition@0 {
47 reg = <0x0 0x00040000>;
54 reg = <0x00040000 0x00040000>;
61 reg = <0x00080000 0x00380000>;
[all …]
H A Dp1020rdb-pd.dts45 reg = <0x0 0xffe05000 0x0 0x1000>;
48 ranges = <0x0 0x0 0x0 0xec000000 0x04000000
49 0x1 0x0 0x0 0xff800000 0x00040000
50 0x2 0x0 0x0 0xffa00000 0x00020000
51 0x3 0x0 0x0 0xffb00000 0x00020000>;
53 nor@0,0 {
57 reg = <0x0 0x0 0x4000000>;
61 partition@0 {
63 reg = <0x0 0x00020000>;
69 reg = <0x00020000 0x003e0000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dfsl,ifc.yaml21 pattern: "^memory-controller@[0-9a-f]+$"
89 reg = <0x0 0xffe1e000 0 0x2000>;
94 ranges = <0x0 0x0 0x0 0xee000000 0x02000000>,
95 <0x1 0x0 0x0 0xffa00000 0x00010000>,
96 <0x3 0x0 0x0 0xffb00000 0x00020000>;
98 flash@0,0 {
102 reg = <0x0 0x0 0x2000000>;
106 partition@0 {
108 reg = <0x0 0x02000000>;
/openbmc/qemu/tests/tcg/hexagon/
H A Dhex_test.h25 printf("ERROR at line %d: 0x%08x != 0x%08x\n", line, val, expect); in __check32()
35 printf("ERROR at line %d: 0x%016llx != 0x%016llx\n", line, val, expect); in __check64()
44 if (ret < 0) { in __chk_error()
55 printf("ERROR at line %d: 0x%p != 0x%p\n", line, p, expect); in __checkp()
65 printf("ERROR at line %d: 0x%08x == 0x%08x\n", line, val, expect); in __check32_ne()
75 printf("ERROR at line %d: 0x%016llx == 0x%016llx\n", line, val, expect); in __check64_ne()
83 #define USR_OVF_BIT 0 /* Sticky saturation overflow */
91 #define USR_CLEAR 0
99 /* Clear bits 0-5 in USR */
102 "r2 = and(r2, #0xffffffc0)\n\t" \
[all …]
/openbmc/u-boot/include/configs/
H A DC29XPCIE.h15 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
26 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
29 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
30 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
36 #define CONFIG_SPL_TEXT_BASE 0xff800000
39 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
40 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
43 #define CONFIG_SPL_PAD_TO 0x20000
44 #define CONFIG_TPL_PAD_TO 0x20000
50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm6125-xiaomi-laurel-sprout.dts21 qcom,msm-id = <394 0>; /* sm6125 v1 */
22 qcom,board-id = <11 0>;
31 reg = <0 0x5c000000 0 (1560 * 720 * 4)>;
41 reg = <0x0 0xffb00000 0x0 0xc0000>;
46 reg = <0x0 0xffbc0000 0x0 0x80000>;
52 reg = <0x0 0xffc40000 0x0 0xc0000>;
53 record-size = <0x1000>;
54 console-size = <0x40000>;
55 pmsg-size = <0x20000>;
59 reg = <0x0 0xffd40000 0x0 0x1000>;
[all …]
H A Dsm6125-sony-xperia-seine-pdx201.dts16 qcom,msm-id = <394 0x10000>; /* sm6125 v1 */
17 qcom,board-id = <34 0>;
35 reg = <0 0x5c000000 0 (2520 * 1080 * 4)>;
51 pinctrl-0 = <&vol_down_n>;
68 reg = <0x0 0xffb00000 0x0 0xc0000>;
73 reg = <0x0 0xffbc0000 0x0 0x80000>;
79 reg = <0x0 0xffc40000 0x0 0xc0000>;
80 record-size = <0x1000>;
81 console-size = <0x40000>;
82 pmsg-size = <0x20000>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_stratix10.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
23 reg = <0x0>;
30 reg = <0x1>;
37 reg = <0x2>;
44 reg = <0x3>;
50 interrupts = <0 120 8>,
51 <0 121 8>,
52 <0 122 8>,
53 <0 123 8>;
[all …]
/openbmc/linux/drivers/mtd/maps/
H A Damd76xrom.c62 module_param(win_size_bits, uint, 0);
63 MODULE_PARM_DESC(win_size_bits, "ROM window size bits override for 0x43 byte, normally set by BIOS.…
76 pci_read_config_byte(window->pdev, 0x40, &byte); in amd76xrom_cleanup()
77 pci_write_config_byte(window->pdev, 0x40, byte & ~1); in amd76xrom_cleanup()
97 window->phys = 0; in amd76xrom_cleanup()
98 window->size = 0; in amd76xrom_cleanup()
123 pci_read_config_byte(pdev, 0x43, &byte); in amd76xrom_init_one()
124 pci_write_config_byte(pdev, 0x43, byte | win_size_bits ); in amd76xrom_init_one()
127 pci_read_config_byte(pdev, 0x43, &byte); in amd76xrom_init_one()
129 window->phys = 0xffb00000; /* 5MiB */ in amd76xrom_init_one()
[all …]
H A Dck804xrom.c68 * byte @0x88: bit 0..7
69 * byte @0x8c: bit 8..15
70 * word @0x90: bit 16..30
72 * Please set win_size_bits to 0x7fffffff if you actually want to do something
74 static uint win_size_bits = 0;
75 module_param(win_size_bits, uint, 0);
89 pci_read_config_byte(window->pdev, 0x6d, &byte); in ck804xrom_cleanup()
90 pci_write_config_byte(window->pdev, 0x6d, byte & ~1); in ck804xrom_cleanup()
109 window->phys = 0; in ck804xrom_cleanup()
110 window->size = 0; in ck804xrom_cleanup()
[all …]

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