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/openbmc/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip,dw-hdmi.yaml31 avdd-0v9-supply:
101 "^port(@0)?$":
107 endpoint@0:
141 reg = <0xff980000 0x20000>;
152 #size-cells = <0>;
154 hdmi_in_vopb: endpoint@0 {
155 reg = <0>;
/openbmc/u-boot/include/configs/
H A DUCP1020.h27 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
80 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
86 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
89 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
92 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
117 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
118 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
120 #define CONFIG_SYS_CCSRBAR 0xffe00000
140 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
146 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
[all …]
H A Dp1_p2_rdb_pc.h16 #define __SW_BOOT_MASK 0x03
17 #define __SW_BOOT_NOR 0xe4
18 #define __SW_BOOT_SD 0x54
24 #define __SW_BOOT_MASK 0x03
25 #define __SW_BOOT_NOR 0xe0
26 #define __SW_BOOT_SD 0x50
35 #define __SW_BOOT_MASK 0x03
36 #define __SW_BOOT_NOR 0x5c
37 #define __SW_BOOT_SPI 0x1c
38 #define __SW_BOOT_SD 0x9c
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3288.dtsi53 #size-cells = <0>;
60 reg = <0x500>;
85 reg = <0x501>;
91 reg = <0x502>;
97 reg = <0x503>;
111 reg = <0xff250000 0x4000>;
122 reg = <0xff600000 0x4000>;
123 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
134 reg = <0xffb20000 0x4000>;
135 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3288.dtsi53 #size-cells = <0>;
60 reg = <0x500>;
71 reg = <0x501>;
82 reg = <0x502>;
93 reg = <0x503>;
103 cpu_opp_table: opp-table-0 {
163 * The rk3288 cannot use the memory area above 0xfe000000
173 reg = <0x0 0xfe000000 0x0 0x1000000>;
181 #clock-cells = <0>;
197 reg = <0x0 0xff810000 0x0 0x20>;
[all …]