Home
last modified time | relevance | path

Searched +full:0 +full:xff900000 (Results 1 – 16 of 16) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dbase_addr_ac5.h9 #define SOCFPGA_FPGA_SLAVES_ADDRESS 0xc0000000
10 #define SOCFPGA_STM_ADDRESS 0xfc000000
11 #define SOCFPGA_DAP_ADDRESS 0xff000000
12 #define SOCFPGA_EMAC0_ADDRESS 0xff700000
13 #define SOCFPGA_EMAC1_ADDRESS 0xff702000
14 #define SOCFPGA_SDMMC_ADDRESS 0xff704000
15 #define SOCFPGA_QSPI_ADDRESS 0xff705000
16 #define SOCFPGA_GPIO0_ADDRESS 0xff708000
17 #define SOCFPGA_GPIO1_ADDRESS 0xff709000
18 #define SOCFPGA_GPIO2_ADDRESS 0xff70a000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Ddenali,nand.yaml141 reg = <0xff900000 0x20>, <0xffb80000 0x1000>;
142 interrupts = <0 144 4>;
148 #size-cells = <0>;
150 nand@0 {
151 reg = <0>;
/openbmc/linux/arch/arm/boot/dts/calxeda/
H A Dhighbank.dts9 /memreserve/ 0x00000000 0x0001000;
19 #size-cells = <0>;
24 reg = <0x900>;
43 reg = <0x901>;
62 reg = <0x902>;
81 reg = <0x903>;
98 memory@0 {
101 reg = <0x00000000 0xff900000>;
105 ranges = <0x00000000 0x00000000 0xffffffff>;
109 reg = <0xfff00000 0x1000>;
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dbvme6000hw.h11 #define BVME_PIT_BASE 0xffa00000
47 #define BVME_RTC_BASE 0xff900000
86 #define BVME_I596_BASE 0xff100000
88 #define BVME_ETHIRQ_REG 0xff20000b
90 #define BVME_LOCAL_IRQ_STAT 0xff20000f
92 #define BVME_ETHERR 0x02
93 #define BVME_ABORT_STATUS 0x08
95 #define BVME_NCR53C710_BASE 0xff000000
97 #define BVME_SCC_A_ADDR 0xffb0000b
98 #define BVME_SCC_B_ADDR 0xffb00003
[all …]
/openbmc/linux/drivers/staging/rtl8192e/rtl8192e/
H A Drtl_core.h58 #define HAL_HW_PCI_REVISION_ID_8192PCIE 0x01
59 #define HAL_HW_PCI_REVISION_ID_8192SE 0x10
76 #define DEFAULT_BEACONINTERVAL 0x64U
102 NIC_UNKNOWN = 0,
118 TXCMD_TXRA_HISTORY_CTRL = 0xFF900000,
119 TXCMD_RESET_TX_PKT_BUFF = 0xFF900001,
120 TXCMD_RESET_RX_PKT_BUFF = 0xFF900002,
121 TXCMD_SET_TX_DURATION = 0xFF900003,
122 TXCMD_SET_RX_RSSI = 0xFF900004,
123 TXCMD_SET_TX_PWR_TRACKING = 0xFF900005,
[all …]
/openbmc/qemu/hw/arm/
H A Dhighbank.c41 #define SMP_BOOT_ADDR 0x100
42 #define SMP_BOOT_REG 0x40
43 #define MPCORE_PERIPHBASE 0xfff10000
45 #define MVBAR_ADDR 0x200
52 #define NUM_REGS 0x200
58 if (offset == 0xf00) { in hb_regs_write()
68 "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset); in hb_regs_write()
82 "highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset); in hb_regs_read()
83 return 0; in hb_regs_read()
87 if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) { in hb_regs_read()
[all …]
/openbmc/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi21 service_reserved: svcbuffer@0 {
23 reg = <0x0 0x0 0x0 0x1000000>;
24 alignment = <0x1000>;
31 #size-cells = <0>;
33 cpu0: cpu@0 {
37 reg = <0x0>;
44 reg = <0x1>;
51 reg = <0x2>;
58 reg = <0x3>;
64 interrupts = <0 170 4>,
[all …]
/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi22 service_reserved: svcbuffer@0 {
24 reg = <0x0 0x0 0x0 0x2000000>;
25 alignment = <0x1000>;
32 #size-cells = <0>;
34 cpu0: cpu@0 {
38 reg = <0x0>;
45 reg = <0x1>;
52 reg = <0x2>;
59 reg = <0x3>;
85 reg = <0x0 0xfffc1000 0x0 0x1000>,
[all …]
/openbmc/linux/arch/arm/mach-orion5x/
H A Dts78xx-setup.c33 #define TS78XX_FPGA_REGS_PHYS_BASE 0xe8000000
34 #define TS78XX_FPGA_REGS_VIRT_BASE IOMEM(0xff900000)
38 .id = 0,
65 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
78 #define TS_RTC_CTRL (TS78XX_FPGA_REGS_PHYS_BASE + 0x808)
79 #define TS_RTC_DATA (TS78XX_FPGA_REGS_PHYS_BASE + 0x80c)
82 DEFINE_RES_MEM(TS_RTC_CTRL, 0x01),
83 DEFINE_RES_MEM(TS_RTC_DATA, 0x01),
97 if (ts78xx_fpga.supports.ts_rtc.init == 0) { in ts78xx_ts_rtc_load()
119 #define TS_NAND_CTRL (TS78XX_FPGA_REGS_VIRT_BASE + 0x800) /* VIRT */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga.dtsi23 #size-cells = <0>;
26 cpu0: cpu@0 {
29 reg = <0>;
43 interrupts = <0 176 4>, <0 177 4>;
45 reg = <0xff111000 0x1000>,
46 <0xff113000 0x1000>;
53 reg = <0xfffed000 0x1000>,
54 <0xfffec100 0x100>;
73 reg = <0xffe01000 0x1000>;
74 interrupts = <0 104 4>,
[all …]
H A Drk3399.dtsi43 #size-cells = <0>;
71 cpu_l0: cpu@0 {
74 reg = <0x0 0x0>;
83 reg = <0x0 0x1>;
91 reg = <0x0 0x2>;
99 reg = <0x0 0x3>;
107 reg = <0x0 0x100>;
116 reg = <0x0 0x101>;
139 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
140 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga.dtsi23 #size-cells = <0>;
26 cpu0: cpu@0 {
29 reg = <0>;
43 interrupts = <0 176 4>, <0 177 4>;
45 reg = <0xff111000 0x1000>,
46 <0xff113000 0x1000>;
53 reg = <0xfffed000 0x1000>,
54 <0xfffec100 0x100>;
73 reg = <0xffe01000 0x1000>;
74 interrupts = <0 104 4>,
[all …]
/openbmc/linux/drivers/staging/rtl8192u/
H A Dr8192U.h57 } while (0)
59 #define COMP_TRACE BIT(0) /* Function call tracing. */
105 } while (0)
117 for (i = 0; i < (int)(datalen); i++) { \
119 if ((i+1)%16 == 0) \
124 } while (0)
126 #define RTL8192U_ASSERT(expr) do {} while (0)
127 #define RT_DEBUG_DATA(level, data, datalen) do {} while (0)
131 #define QSLT_BK 0x1
132 #define QSLT_BE 0x0
[all …]
/openbmc/qemu/hw/sh4/
H A Dsh7750_regs.h42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
45 #define SH7750_P4_BASE 0xff000000 /* Accessible only in privileged mode */
46 #define SH7750_A7_BASE 0x1f000000 /* Accessible only using TLB */
56 #define SH7750_PTEH_REGOFS 0x000000 /* offset */
59 #define SH7750_PTEH_VPN 0xfffffd00 /* Virtual page number */
61 #define SH7750_PTEH_ASID 0x000000ff /* Address space identifier */
62 #define SH7750_PTEH_ASID_S 0
65 #define SH7750_PTEL_REGOFS 0x000004 /* offset */
68 #define SH7750_PTEL_PPN 0x1ffffc00 /* Physical page number */
[all …]
/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12-common.dtsi107 reg = <0x0 0x05000000 0x0 0x300000>;
113 reg = <0x0 0x05300000 0x0 0x2000000>;
120 size = <0x0 0x10000000>;
121 alignment = <0x0 0x400000>;
138 reg = <0x0 0xfc000000 0x0 0x400000>,
139 <0x0 0xff648000 0x0 0x2000>,
140 <0x0 0xfc400000 0x0 0x200000>;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
146 bus-range = <0x0 0xff>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399.dtsi41 #size-cells = <0>;
69 cpu_l0: cpu@0 {
72 reg = <0x0 0x0>;
84 reg = <0x0 0x1>;
96 reg = <0x0 0x2>;
108 reg = <0x0 0x3>;
120 reg = <0x0 0x100>;
138 reg = <0x0 0x101>;
159 arm,psci-suspend-param = <0x0010000>;
168 arm,psci-suspend-param = <0x1010000>;
[all …]