Searched +full:0 +full:xff640000 (Results 1 – 5 of 5) sorted by relevance
36 const: 062 reg = <0xff640000 0x100>;69 #phy-cells = <0>;
13 pclk_ddrupctl0: support clock for access protocol controller registers of channel 014 pclk_publ0: support clock for access phy controller registers of channel 025 …t * 32 * n_clk cycles.The automatic self refresh function is disabled when auto-self-refresh-cnt=0.26 …wer-down-cnt n_clk cycles.The automatic power down function is disabled when auto-power-down-cnt=0.28 0.DDR3_800D (5-5-5)110 odt - 1 to enable DDR ODT, 0 to disable120 reg = <0xff610000 0x3fc121 0xff620000 0x294122 0xff630000 0x3fc123 0xff640000 0x294>;[all …]
28 #size-cells = <0>;33 reg = <0xf00>;41 reg = <0xf01>;49 reg = <0xf02>;57 reg = <0xf03>;95 #clock-cells = <0>;100 reg = <0xfe000000 0x20000>;105 reg = <0xfe020000 0x1000>;115 reg = <0xfe860000 0x20>;120 reg = <0xfe860080 0x20>;[all …]
24 tdmif_a: audio-controller-0 {26 #sound-dai-cells = <0>;37 #sound-dai-cells = <0>;48 #sound-dai-cells = <0>;67 #address-cells = <0x2>;68 #size-cells = <0x0>;70 cpu0: cpu@0 {73 reg = <0x0 0x0>;76 clocks = <&scpi_dvfs 0>;82 reg = <0x0 0x1>;[all …]
53 #size-cells = <0>;60 reg = <0x500>;85 reg = <0x501>;91 reg = <0x502>;97 reg = <0x503>;111 reg = <0xff250000 0x4000>;122 reg = <0xff600000 0x4000>;123 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,134 reg = <0xffb20000 0x4000>;135 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,[all …]