Searched +full:0 +full:xfd7c0000 (Results 1 – 3 of 3) sorted by relevance
/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | rockchip,rk3588-cru.yaml | 68 reg = <0xfd7c0000 0x5c000>;
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/openbmc/linux/drivers/clk/rockchip/ |
H A D | rst-rk3588.c | 13 /* 0xFD7C0000 + 0x0A00 */ 14 #define RK3588_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) 16 /* 0xFD7C8000 + 0x0A00 */ 17 #define RK3588_PHPTOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit) 19 /* 0xFD7D0000 + 0x0A00 */ 20 #define RK3588_SECURECRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit) 22 /* 0xFD7F0000 + 0x0A00 */ 23 #define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit) 37 RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M400_BIU, 2, 0), 48 RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_CMN, 3, 0), [all …]
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/openbmc/linux/arch/arm64/boot/dts/rockchip/ |
H A D | rk3588s.dtsi | 23 #size-cells = <0>; 58 cpu_l0: cpu@0 { 61 reg = <0x0>; 82 reg = <0x100>; 101 reg = <0x200>; 120 reg = <0x300>; 139 reg = <0x400>; 160 reg = <0x500>; 179 reg = <0x600>; 200 reg = <0x700>; [all …]
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