Home
last modified time | relevance | path

Searched +full:0 +full:xfc000000 (Results 1 – 25 of 215) sorted by relevance

123456789

/openbmc/u-boot/board/sbc8548/
H A Dtlb.c13 /* TLB 0 - for temp stack in cache */
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
15 MAS3_SX|MAS3_SW|MAS3_SR, 0,
16 0, 0, BOOKE_PAGESZ_4K, 0),
17 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
19 MAS3_SX|MAS3_SW|MAS3_SR, 0,
20 0, 0, BOOKE_PAGESZ_4K, 0),
21 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
23 MAS3_SX|MAS3_SW|MAS3_SR, 0,
24 0, 0, BOOKE_PAGESZ_4K, 0),
[all …]
/openbmc/linux/arch/arm/mach-spear/
H A Dspear.h18 #define SPEAR_ICM1_2_BASE UL(0xD0000000)
19 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
20 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)
22 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
25 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
26 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
29 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
30 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
31 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
32 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
[all …]
H A Dspear3xx.c26 .bus_id = 0,
48 * 0xD0000000 0xFD000000
49 * 0xFC000000 0xFC000000
/openbmc/qemu/disas/
H A Dhppa.c50 #define PA_PAGESIZE 0x1000
59 R_HPPA_FSEL = 0x0,
60 R_HPPA_LSSEL = 0x1,
61 R_HPPA_RSSEL = 0x2,
62 R_HPPA_LSEL = 0x3,
63 R_HPPA_RSEL = 0x4,
64 R_HPPA_LDSEL = 0x5,
65 R_HPPA_RDSEL = 0x6,
66 R_HPPA_LRSEL = 0x7,
67 R_HPPA_RRSEL = 0x8,
[all …]
H A Dmips.c82 #define OP_MASK_OP 0x3f
84 #define OP_MASK_RS 0x1f
86 #define OP_MASK_FR 0x1f
88 #define OP_MASK_FMT 0x1f
90 #define OP_MASK_BCC 0x7
92 #define OP_MASK_CODE 0x3ff
94 #define OP_MASK_CODE2 0x3ff
96 #define OP_MASK_RT 0x1f
98 #define OP_MASK_FT 0x1f
100 #define OP_MASK_CACHE 0x1f
[all …]
/openbmc/linux/arch/arm/crypto/
H A Dpoly1305-armv4.pl28 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
38 ($ctx,$inp,$len,$padbit)=map("r$_",(0..3));
71 cmp $inp,#0
72 str r3,[$ctx,#0] @ zero hash value
83 moveq r0,#0
94 ldrb r4,[$inp,#0]
95 mov r10,#0x0fffffff
97 and r3,r10,#-4 @ 0x0ffffffc
153 str r4,[$ctx,#0]
164 mov r0,#0
[all …]
/openbmc/qemu/hw/misc/
H A Dxlnx-versal-pmc-iou-slcr.c37 #define XILINX_VERSAL_PMC_IOU_SLCR_ERR_DEBUG 0
40 REG32(MIO_PIN_0, 0x0)
45 REG32(MIO_PIN_1, 0x4)
50 REG32(MIO_PIN_2, 0x8)
55 REG32(MIO_PIN_3, 0xc)
60 REG32(MIO_PIN_4, 0x10)
65 REG32(MIO_PIN_5, 0x14)
70 REG32(MIO_PIN_6, 0x18)
75 REG32(MIO_PIN_7, 0x1c)
80 REG32(MIO_PIN_8, 0x20)
[all …]
/openbmc/linux/arch/arm/mach-footbridge/include/mach/
H A Dhardware.h13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
24 #define XBUS_SIZE 0x00100000
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
/openbmc/u-boot/board/micronas/vct/
H A Debi_nor_flash.c12 addr &= ~0xFC000000; in ebi_read()
24 addr &= ~0xFC000000; in ebi_write_u16()
34 u32 counter = 0; in ebi_write_u16()
36 if (counter++ > 0xFFFFFF) in ebi_write_u16()
41 return 0; in ebi_write_u16()
46 return ((ebi_read(addr) >> 16) & 0xFFFF); in ebi_read_u16()
53 if (addr & 0x1) in ebi_read_u8()
54 return val & 0xff; in ebi_read_u8()
56 return (val >> 8) & 0xff; in ebi_read_u8()
64 reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); in ebi_init_nor_flash()
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dprobes.h17 #define IS_TW(instr) (((instr) & 0xfc0007fe) == 0x7c000008)
18 #define IS_TD(instr) (((instr) & 0xfc0007fe) == 0x7c000088)
19 #define IS_TDI(instr) (((instr) & 0xfc000000) == 0x08000000)
20 #define IS_TWI(instr) (((instr) & 0xfc000000) == 0x0c000000)
/openbmc/linux/net/netfilter/ipset/
H A Dpfxlen.c12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dstorcenter.dts30 #size-cells = <0>;
32 PowerPC,8241@0 {
34 reg = <0>;
37 bus-frequency = <0>; /* from bootwrapper */
47 reg = <0x00000000 0x04000000>; /* 64MB @ 0x0 */
55 store-gathering = <0>; /* 0 == off, !0 == on */
56 ranges = <0x0 0xfc000000 0x100000>;
57 reg = <0xfc000000 0x100000>; /* EUMB */
58 bus-frequency = <0>; /* fixed by loader */
62 #size-cells = <0>;
[all …]
H A DkuroboxHG.dts37 #size-cells = <0>;
41 reg = <0x0>;
44 bus-frequency = <0>; /* Fixed by bootloader */
46 i-cache-size = <0x4000>;
47 d-cache-size = <0x4000>;
53 reg = <0x0 0x8000000>;
61 store-gathering = <0>; /* 0 == off, !0 == on */
62 reg = <0x80000000 0x100000>;
63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
64 0xfc000000 0xfc000000 0x100000 /* EUMB */
[all …]
H A DkuroboxHD.dts37 #size-cells = <0>;
41 reg = <0x0>;
44 bus-frequency = <0>; /* Fixed by bootloader */
46 i-cache-size = <0x4000>;
47 d-cache-size = <0x4000>;
53 reg = <0x0 0x4000000>;
61 store-gathering = <0>; /* 0 == off, !0 == on */
62 reg = <0x80000000 0x100000>;
63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
64 0xfc000000 0xfc000000 0x100000 /* EUMB */
[all …]
H A Do2dnt2.dts15 memory@0 {
16 reg = <0x00000000 0x08000000>; // 128MB
20 ranges = <0 0 0xfc000000 0x02000000
21 3 0 0xe3000000 0x00100000>;
23 flash@0,0 {
25 reg = <0 0 0x02000000>;
33 reg = <0x00060000 0x00260000>;
40 reg = <0x002c0000 0x01d40000>;
H A Do2d.dts15 memory@0 {
16 reg = <0x00000000 0x08000000>; // 128MB
20 ranges = <0 0 0xfc000000 0x02000000
21 3 0 0xe3000000 0x00100000>;
23 flash@0,0 {
25 reg = <0 0 0x02000000>;
33 reg = <0x00060000 0x00260000>;
39 reg = <0x002c0000 0x01d40000>;
/openbmc/linux/include/linux/ssb/
H A Dssb_driver_pci.h13 #define SSB_PCICORE_CTL 0x0000 /* PCI Control */
14 #define SSB_PCICORE_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */
15 #define SSB_PCICORE_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */
16 #define SSB_PCICORE_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */
17 #define SSB_PCICORE_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */
18 #define SSB_PCICORE_ARBCTL 0x0010 /* PCI Arbiter Control */
19 #define SSB_PCICORE_ARBCTL_INTERN 0x00000001 /* Use internal arbiter */
20 #define SSB_PCICORE_ARBCTL_EXTERN 0x00000002 /* Use external arbiter */
21 #define SSB_PCICORE_ARBCTL_PARKID 0x00000006 /* Mask, selects which agent is parked on an idle bus…
22 #define SSB_PCICORE_ARBCTL_PARKID_LAST 0x00000000 /* Last requestor */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/thermal/
H A Dspear-thermal.txt12 reg = <0xfc000000 0x1000>;
13 st,thermal-flags = <0x7000>;
/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Dspear-rtc.txt12 reg = <0xfc000000 0x1000>;
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-spear.txt16 reg = <0xfc000000 0x1000>;
17 cd-gpios = <&gpio0 6 0>;
/openbmc/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dhandles.h10 #define NV50_DISP_HANDLE_SYNCBUF 0xf0000000
11 #define NV50_DISP_HANDLE_VRAM 0xf0000001
13 #define NV50_DISP_HANDLE_WNDW_CTX(kind) (0xfb000000 | kind)
14 #define NV50_DISP_HANDLE_CRC_CTX(head, i) (0xfc000000 | head->base.index << 1 | i)
/openbmc/qemu/include/hw/xen/interface/arch-x86/
H A Dxen-x86_32.h27 #define FLAT_RING1_CS 0xe019 /* GDT index 259 */
28 #define FLAT_RING1_DS 0xe021 /* GDT index 260 */
29 #define FLAT_RING1_SS 0xe021 /* GDT index 260 */
30 #define FLAT_RING3_CS 0xe02b /* GDT index 261 */
31 #define FLAT_RING3_DS 0xe033 /* GDT index 262 */
32 #define FLAT_RING3_SS 0xe033 /* GDT index 262 */
41 #define __HYPERVISOR_VIRT_START_PAE 0xF5800000
42 #define __MACH2PHYS_VIRT_START_PAE 0xF5800000
43 #define __MACH2PHYS_VIRT_END_PAE 0xF6800000
49 #define __HYPERVISOR_VIRT_START_NONPAE 0xFC000000
[all …]
/openbmc/u-boot/configs/
H A Dmpc8308_p1m_defconfig2 CONFIG_SYS_TEXT_BASE=0xFC000000
/openbmc/qemu/include/hw/arm/
H A Dbcm2838.h16 #define BCM2838_PERI_LOW_BASE 0xfc000000
17 #define BCM2838_GIC_BASE 0x40000

123456789