Searched +full:0 +full:xfb400000 (Results 1 – 5 of 5) sorted by relevance
| /openbmc/u-boot/arch/mips/dts/ |
| H A D | ci20.dts | 23 reg = <0x0 0x10000000
24 0x30000000 0x30000000>;
53 reg = <1 0 0x1000000>;
56 #size-cells = <0>;
79 partition@0 {
81 reg = <0x0 0x0 0x0 0x800000>;
84 partition@0x800000 {
86 reg = <0x0 0x800000 0x0 0x200000>;
89 partition@0xa00000 {
91 reg = <0x0 0xa00000 0x0 0x200000>;
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/mtd/ |
| H A D | ingenic,nand.yaml | 66 reg = <0x13410000 0x10000>;
69 ranges = <1 0 0x1b000000 0x1000000>,
70 <2 0 0x1a000000 0x1000000>,
71 <3 0 0x19000000 0x1000000>,
72 <4 0 0x18000000 0x1000000>,
73 <5 0 0x17000000 0x1000000>,
74 <6 0 0x16000000 0x1000000>;
80 reg = <1 0 0x1000000>;
83 #size-cells = <0>;
94 pinctrl-0 = <&pins_nemc>;
[all …]
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| /openbmc/u-boot/arch/arm/mach-rmobile/include/mach/ |
| H A D | sh73a0.h | 5 #define GLOBAL_TIMER_BASE_ADDR (0xF0000200)
6 #define MERAM_BASE (0xE5580000)
9 #define GIC_BASE (0xF0000100)
13 #define LIFEC_SEC_SRC (0xE6110008)
16 #define RWDT_BASE (0xE6020000)
19 #define HPB_BASE (0xE6001010)
22 #define HPBSCR_BASE (0xE6001600)
25 #define SBSC1_BASE (0xFE400000)
26 #define SDMRA1A (SBSC1_BASE + 0x100000)
27 #define SDMRA2A (SBSC1_BASE + 0x1C0000)
[all …]
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| /openbmc/linux/arch/mips/boot/dts/ingenic/ |
| H A D | ci20.dts | 27 reg = <0x0 0x10000000
28 0x30000000 0x30000000>;
45 led-0 {
65 gpios = <&gpc 0 GPIO_ACTIVE_HIGH>;
70 eth0_power: fixedregulator-0 {
77 gpio = <&gpb 25 0>;
110 gpio = <&gpb 19 0>;
121 gpio = <&gpf 15 0>;
172 assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>,
175 <0>, <&cgu JZ4780_CLK_MPLL>;
[all …]
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| /openbmc/linux/arch/arm/boot/dts/renesas/ |
| H A D | sh73a0.dtsi | 20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0>;
44 reg = <0xf0000200 0x100>;
51 reg = <0xf0000600 0x20>;
60 reg = <0xf0001000 0x1000>,
61 <0xf0000100 0x100>;
66 reg = <0xf0100000 0x1000>;
78 reg = <0xfb400000 0x400>;
87 reg = <0xfe400000 0x400>;
[all …]
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