Home
last modified time | relevance | path

Searched +full:0 +full:xf8018000 (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Datmel,sama5d2-pdmic.yaml61 default: 0
84 reg = <0xf8018000 0x124>;
87 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
93 pinctrl-0 = <&pinctrl_pdmic_default>;
97 atmel,mic-offset = <0x0>;
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91sam9x5.h17 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
23 #define ATMEL_ID_USART0 5 /* USART 0 */
27 #define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */
30 #define ATMEL_ID_HSMCI0 12 /* High Speed Multimedia Card Interface 0 */
31 #define ATMEL_ID_SPI0 13 /* Serial Peripheral Interface 0 */
33 #define ATMEL_ID_UART0 15 /* UART 0 */
35 #define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
38 #define ATMEL_ID_DMAC0 20 /* DMA Controller 0 */
53 #define ATMEL_BASE_SPI0 0xf0000000
54 #define ATMEL_BASE_SPI1 0xf0004000
[all …]
H A Dsama5d3.h18 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
30 #define ATMEL_ID_USART0 12 /* USART 0 */
36 #define ATMEL_ID_TWI0 18 /* Two-Wire Interface 0 */
39 #define ATMEL_ID_MCI0 21 /* High Speed Multimedia Card Interface 0 */
42 #define ATMEL_ID_SPI0 24 /* Serial Peripheral Interface 0 */
56 #define ATMEL_ID_SSC0 38 /* Synchronous Serial Controller 0 */
70 #define ARCH_ID_SAMA5D3 0x8a5c07c0
71 #define ARCH_EXID_SAMA5D31 0x00444300
72 #define ARCH_EXID_SAMA5D33 0x00414300
73 #define ARCH_EXID_SAMA5D34 0x00414301
[all …]
H A Dsama5d4.h15 #define ATMEL_ID_FIQ 0 /* FIQ Interrupt */
21 #define ATMEL_ID_USART0 6 /* USART 0 */
23 #define ATMEL_ID_DMA0 8 /* DMA Controller 0 */
40 #define ATMEL_ID_UART0 27 /* UART 0 */
45 #define ATMEL_ID_TWI0 32 /* Two-Wire Interface 0 */
48 #define ATMEL_ID_MCI0 35 /* High Speed Multimedia Card Interface 0 */
50 #define ATMEL_ID_SPI0 37 /* Serial Peripheral Interface 0 */
53 #define ATMEL_ID_TC0 40 /* Timer Counter 0 (ch. 0, 1, 2) */
61 #define ATMEL_ID_SSC0 48 /* Synchronous Serial Controller 0 */
67 #define ATMEL_ID_GMAC0 54 /* Ethernet MAC 0 */
[all …]
/openbmc/linux/arch/mips/kernel/
H A Dsmp-bmips.c50 #define RESET_FROM_KSEG0 0x80080800
51 #define RESET_FROM_KSEG1 0xa0080800
68 /* SW interrupts 0,1 are used for interprocessor signaling */
69 #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
73 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
74 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
75 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
79 int i, cpu = 1, boot_cpu = 0; in bmips_smp_setup()
86 clear_c0_brcm_cmt_ctrl(0x30); in bmips_smp_setup()
89 set_c0_brcm_config_0(0x30000); in bmips_smp_setup()
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dsam9x60.dtsi37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x20000000 0x10000000>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x00300000 0x100000>;
68 ranges = <0 0x00300000 0x100000>;
79 #size-cells = <0>;
81 reg = <0x00500000 0x100000
[all …]
H A Dat91sam9x5.dtsi44 #size-cells = <0>;
46 cpu@0 {
49 reg = <0>;
55 reg = <0x20000000 0x10000000>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
73 #clock-cells = <0>;
80 reg = <0x00300000 0x8000>;
[all …]
H A Dsama5d2.dtsi29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
41 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
46 reg = <0x740000 0x1000>;
62 reg = <0x73c000 0x1000>;
78 reg = <0x20000000 0x20000000>;
84 #clock-cells = <0>;
85 clock-frequency = <0>;
90 #clock-cells = <0>;
[all …]
H A Dsama5d3.dtsi46 #size-cells = <0>;
47 cpu@0 {
50 reg = <0x0>;
56 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
61 reg = <0x20000000 0x8000000>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
73 #clock-cells = <0>;
74 clock-frequency = <0>;
79 #clock-cells = <0>;
[all …]
H A Dsama5d4.dtsi47 #size-cells = <0>;
49 cpu@0 {
52 reg = <0>;
59 reg = <0x20000000 0x20000000>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
72 clock-frequency = <0>;
77 #clock-cells = <0>;
84 reg = <0x00210000 0x10000>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dat91sam9x5.dtsi51 reg = <0x20000000 0x10000000>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
63 #clock-cells = <0>;
64 clock-frequency = <0>;
69 #clock-cells = <0>;
76 reg = <0x00300000 0x8000>;
97 reg = <0xfffff000 0x200>;
103 reg = <0xffffe800 0x200>;
110 reg = <0xfffffc00 0x200>;
[all …]
H A Dsama5d3.dtsi45 #size-cells = <0>;
46 cpu@0 {
49 reg = <0x0>;
55 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
59 reg = <0x20000000 0x8000000>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
72 clock-frequency = <0>;
77 #clock-cells = <0>;
[all …]
H A Dsama5d4.dtsi82 #size-cells = <0>;
84 cpu@0 {
87 reg = <0>;
93 reg = <0x20000000 0x20000000>;
99 #clock-cells = <0>;
100 clock-frequency = <0>;
105 #clock-cells = <0>;
106 clock-frequency = <0>;
111 #clock-cells = <0>;
118 reg = <0x00210000 0x10000>;
[all …]