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/openbmc/u-boot/arch/x86/cpu/
H A Dioapic.c31 debug("IOAPIC: ID = 0x%02x\n", ioapic_id); in io_apic_set_id()
33 io_apic_write(0x00, (io_apic_read(0x00) & 0xf0ffffff) | in io_apic_set_id()
/openbmc/linux/arch/mips/boot/dts/loongson/
H A Dloongson64c-package.dtsi10 #address-cells = <0>;
20 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
21 0 0x3ff00000 0 0x3ff00000 0x100000
23 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000
25 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000>;
29 reg = <0 0x3ff01400 0x64>;
38 loongson,parent_int_map = <0xf0ffffff>, /* int0 */
39 <0x0f000000>, /* int1 */
40 <0x00000000>, /* int2 */
41 <0x00000000>; /* int3 */
[all …]
/openbmc/u-boot/doc/mvebu/
H A Darmada-8k-memory.txt13 0x00000000 0xEFFFFFFF DRAM
15 0xF0000000 0xF0FFFFFF AP Internal registers space
17 0xF1000000 0xF1FFFFFF Reserved.
19 0xF2000000 0xF3FFFFFF CP-0 Internal (configuration) registers
22 0xF4000000 0xF5FFFFFF CP-1 Internal (configuration) registers
25 0xF6000000 0xF6FFFFFF CP-0 / PCIe#0 Memory space.
27 0xF7000000 0xF7FFFFFF CP-0 / PCIe#1 Memory space.
29 0xF8000000 0xF8FFFFFF CP-0 / PCIe#2 Memory space.
31 0xF9000000 0xF900FFFF CP-0 / PCIe#0 IO space.
33 0xF9010000 0xF901FFFF CP-0 / PCIe#1 IO space.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dloongson,liointc.yaml60 interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
61 and each bit in the cell refers to a child interrupt from 0 to 31.
103 reg = <0x3ff01400 0x64>;
112 loongson,parent_int_map = <0xf0ffffff>, /* int0 */
113 <0x0f000000>, /* int1 */
114 <0x00000000>, /* int2 */
115 <0x00000000>; /* int3 */
/openbmc/linux/arch/parisc/kernel/
H A Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
/openbmc/u-boot/arch/m68k/include/asm/coldfire/
H A Dssi.h23 u8 resv0[0x4];
25 u8 resv1[0x8];
34 #define SSI_CR_CIS (0x00000200)
35 #define SSI_CR_TCH (0x00000100)
36 #define SSI_CR_MCE (0x00000080)
37 #define SSI_CR_I2S_MASK (0xFFFFFF9F)
38 #define SSI_CR_I2S_SLAVE (0x00000040)
39 #define SSI_CR_I2S_MASTER (0x00000020)
40 #define SSI_CR_I2S_NORMAL (0x00000000)
41 #define SSI_CR_SYN (0x00000010)
[all …]
/openbmc/linux/arch/arm/mach-zynq/
H A Dslcr.c17 #define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */
18 #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */
19 #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
20 #define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */
21 #define SLCR_PSS_IDCODE 0x530 /* PS IDCODE */
22 #define SLCR_L2C_RAM 0xA1C /* L2C_RAM in AR#54190 */
24 #define SLCR_UNLOCK_MAGIC 0xDF0D
25 #define SLCR_A9_CPU_CLKSTOP 0x10
26 #define SLCR_A9_CPU_RST 0x1
28 #define SLCR_PSS_IDCODE_DEVICE_MASK 0x1F
[all …]
/openbmc/linux/arch/powerpc/include/asm/book3s/32/
H A Dmmu-hash.h14 #define BL_128K 0x000
15 #define BL_256K 0x001
16 #define BL_512K 0x003
17 #define BL_1M 0x007
18 #define BL_2M 0x00F
19 #define BL_4M 0x01F
20 #define BL_8M 0x03F
21 #define BL_16M 0x07F
22 #define BL_32M 0x0FF
23 #define BL_64M 0x1FF
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dmmci.c371 int busy = 0; in mmci_card_busy()
441 host->cclk = 0; in mmci_set_clkreg()
525 return 0; in mmci_validate_data()
535 return 0; in mmci_validate_data()
543 return 0; in mmci_prep_data()
548 data->host_cookie = ++host->next_cookie < 0 ? in mmci_prep_data()
560 data->host_cookie = 0; in mmci_unprep_data()
605 return 0; in mmci_dma_start()
629 writel(0, host->base + MMCICOMMAND); in mmci_request_end()
661 mmci_write_datactrlreg(host, 0); in mmci_stop_data()
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Drs690d.h32 #define R_00001E_K8_FB_LOCATION 0x00001E
33 #define R_00005F_MC_MISC_UMA_CNTL 0x00005F
34 #define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF)
35 #define R_000078_MC_INDEX 0x000078
36 #define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0)
37 #define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF)
38 #define C_000078_MC_IND_ADDR 0xFFFFFE00
39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9)
40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1)
41 #define C_000078_MC_IND_WR_EN 0xFFFFFDFF
[all …]
H A Dr600d.h30 #define CP_PACKET2 0x80000000
31 #define PACKET2_PAD_SHIFT 0
32 #define PACKET2_PAD_MASK (0x3fffffff << 0)
41 #define R6XX_MAX_BACKENDS_MASK 0xff
43 #define R6XX_MAX_SIMDS_MASK 0xff
45 #define R6XX_MAX_PIPES_MASK 0xff
48 #define ARRAY_LINEAR_GENERAL 0x00000000
49 #define ARRAY_LINEAR_ALIGNED 0x00000001
50 #define ARRAY_1D_TILED_THIN1 0x00000002
51 #define ARRAY_2D_TILED_THIN1 0x00000004
[all …]
/openbmc/u-boot/arch/m68k/include/asm/
H A Dm5441x.h13 #define INT0_LO_RSVD0 (0)
78 #define INT1_LO_CAN0_IFG (0)
141 #define INT2_LO_EDMA56_63 (0)
191 #define SBF_SBFCR_BLDIV(x) (((x)&0x000F))
192 #define SBF_SBFCR_FR (0x0010)
195 #define RCM_RCR_SOFTRST (0x80)
196 #define RCM_RCR_FRCRSTOUT (0x40)
198 #define RCM_RSR_SOFT (0x20)
199 #define RCM_RSR_LOC (0x10)
200 #define RCM_RSR_POR (0x08)
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/openbmc/linux/drivers/video/fbdev/sis/
H A Dinit.c94 #if 0 in InitCommonPointer()
144 #if 0 in InitCommonPointer()
344 unsigned short ModeIndex = 0; in SiS_GetModeID()
483 unsigned short ModeIndex = 0; in SiS_GetModeID_LCD()
732 unsigned short ModeIndex = 0; in SiS_GetModeID_TV()
851 if(!(VBFlags2 & VB2_SISVGA2BRIDGE)) return 0; in SiS_GetModeID_VGA2()
853 if(HDisplay >= 1920) return 0; in SiS_GetModeID_VGA2()
859 if(VGAEngine != SIS_315_VGA) return 0; in SiS_GetModeID_VGA2()
860 if(!(VBFlags2 & VB2_30xB)) return 0; in SiS_GetModeID_VGA2()
865 if(VGAEngine != SIS_315_VGA) return 0; in SiS_GetModeID_VGA2()
[all …]
/openbmc/linux/sound/pci/au88x0/
H A Dau88x0_core.c80 hwread(vortex->mmio, VORTEX_MIXER_SR) | (0x1 << channel)); in vortex_mixer_en_sr()
85 hwread(vortex->mmio, VORTEX_MIXER_SR) & ~(0x1 << channel)); in vortex_mixer_dis_sr()
88 #if 0
94 0x80);
96 0x80);
102 a = hwread(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2)) & 0xff;
113 return 0;
117 if (rampchs[mix] == 0)
123 return (0);
136 for (ch = 0; ch < 0x20; ch++) {
[all …]
/openbmc/linux/drivers/video/fbdev/aty/
H A Datyfb_base.c118 } while (0)
125 } while (0)
144 0, /* EXT_VERT_STRETCH */
185 return 0; in aty_ld_lcd()
288 640, 480, 640, 480, 0, 0, 8, 0,
289 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
290 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
291 0, FB_VMODE_NONINTERLACED
297 0, FB_VMODE_NONINTERLACED
336 module_param_named(vmode, default_vmode, int, 0);
[all …]
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.c54 OPC_SPECIAL = (0x00 << 26),
55 OPC_REGIMM = (0x01 << 26),
56 OPC_CP0 = (0x10 << 26),
57 OPC_CP2 = (0x12 << 26),
58 OPC_CP3 = (0x13 << 26),
59 OPC_SPECIAL2 = (0x1C << 26),
60 OPC_SPECIAL3 = (0x1F << 26),
62 OPC_ADDI = (0x08 << 26),
63 OPC_ADDIU = (0x09 << 26),
64 OPC_SLTI = (0x0A << 26),
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Dcoex.c75 rtw_write8_set(rtwdev, REG_LIFETIME_EN, 0xf); in rtw_coex_limited_tx()
76 rtw_write16(rtwdev, REG_RETRY_LIMIT, 0x0808); in rtw_coex_limited_tx()
79 rtw_write32(rtwdev, REG_DARFRC, 0x1000000); in rtw_coex_limited_tx()
80 rtw_write32(rtwdev, REG_DARFRCH, 0x4030201); in rtw_coex_limited_tx()
83 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, 0xf); in rtw_coex_limited_tx()
91 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, 0x20); in rtw_coex_limited_tx()
132 COEX_RSSI_HIGH(coex_dm->bt_rssi_state[0])) in rtw_coex_freerun_check()
136 bt_rssi = coex_dm->bt_rssi_state[0]; in rtw_coex_freerun_check()
152 u8 para[6] = {0}; in rtw_coex_wl_slot_extend()
154 para[0] = COEX_H2C69_WL_LEAKAP; in rtw_coex_wl_slot_extend()
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Dreg.h8 #define R_AX_SYS_WL_EFUSE_CTRL 0x000A
11 #define R_AX_SYS_ISO_CTRL 0x0000
17 #define R_AX_SYS_FUNC_EN 0x0002
19 #define B_AX_FEN_BBRSTB BIT(0)
21 #define R_AX_SYS_PW_CTRL 0x0004
36 #define R_AX_SYS_CLK_CTRL 0x0008
39 #define R_AX_SYS_SWR_CTRL1 0x0010
42 #define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018
46 #define R_AX_RSV_CTRL 0x001C
50 #define R_AX_AFE_LDO_CTRL 0x0020
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c56 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
57 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388
59 #define regCGTT_WD_CLK_CTRL 0x5086
61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e
87 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)
92 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
93 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010),
94 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
95 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988),
96 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007),
[all …]