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/openbmc/linux/include/misc/
H A Docxl-config.h13 #define OCXL_EXT_CAP_ID_DVSEC 0x23
15 #define OCXL_DVSEC_VENDOR_OFFSET 0x4
16 #define OCXL_DVSEC_ID_OFFSET 0x8
17 #define OCXL_DVSEC_TL_ID 0xF000
18 #define OCXL_DVSEC_TL_BACKOFF_TIMERS 0x10
19 #define OCXL_DVSEC_TL_RECV_CAP 0x18
20 #define OCXL_DVSEC_TL_SEND_CAP 0x20
21 #define OCXL_DVSEC_TL_RECV_RATE 0x30
22 #define OCXL_DVSEC_TL_SEND_RATE 0x50
23 #define OCXL_DVSEC_FUNC_ID 0xF001
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dwm2000.h9 #define WM2000_REG_SYS_START 0x8000
10 #define WM2000_REG_ANC_GAIN_CTRL 0x8fa2
11 #define WM2000_REG_MSE_TH2 0x8fdf
12 #define WM2000_REG_MSE_TH1 0x8fe0
13 #define WM2000_REG_SPEECH_CLARITY 0x8fef
14 #define WM2000_REG_SYS_WATCHDOG 0x8ff6
15 #define WM2000_REG_ANA_VMID_PD_TIME 0x8ff7
16 #define WM2000_REG_ANA_VMID_PU_TIME 0x8ff8
17 #define WM2000_REG_CAT_FLTR_INDX 0x8ff9
18 #define WM2000_REG_CAT_GAIN_0 0x8ffa
[all …]
/openbmc/linux/drivers/gpu/drm/ast/
H A Dast_main.c45 return !!(ch & 0x01); in ast_is_vga_enabled()
52 ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01); in ast_enable_vga()
53 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01); in ast_enable_vga()
65 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04); in ast_enable_mmio_release()
72 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06); in ast_enable_mmio()
79 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8); in ast_open_key()
87 uint32_t scu_rev = 0xffffffff; in ast_device_config_init()
104 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge in ast_device_config_init()
108 jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_device_config_init()
109 jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); in ast_device_config_init()
[all …]
H A Dast_dp501.c34 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_ack()
35 sendack |= 0x80; in send_ack()
36 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_ack()
42 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_nack()
43 sendack &= ~0x80; in send_nack()
44 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_nack()
50 u32 retry = 0; in wait_ack()
52 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff); in wait_ack()
53 waitack &= 0x80; in wait_ack()
66 u32 retry = 0; in wait_nack()
[all …]
H A Dast_post.c40 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
41 static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
51 for (i = 0x81; i <= 0x9f; i++) in ast_set_def_ext_reg()
52 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); in ast_set_def_ext_reg()
59 index = 0xa0; in ast_set_def_ext_reg()
60 while (*ext_reg_info != 0xff) { in ast_set_def_ext_reg()
61 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info); in ast_set_def_ext_reg()
67 /* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */ in ast_set_def_ext_reg()
70 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01); in ast_set_def_ext_reg()
71 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00); in ast_set_def_ext_reg()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_reg_defs.h14 * @__n: 0-based bit number
23 ((__n) < 0 || (__n) > 31))))
27 * @__n: 0-based bit number
36 ((__n) < 0 || (__n) > 7))))
40 * @__high: 0-based high bit
41 * @__low: 0-based low bit
51 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
55 * @__high: 0-based high bit
56 * @__low: 0-based low bit
66 ((__low) < 0 || (__high) > 63 || (__low) > (__high)))))
[all …]
/openbmc/linux/drivers/dma/ti/
H A Dk3-psil-am654.c54 PSIL_SA2UL(0x4000, 0),
55 PSIL_SA2UL(0x4001, 0),
56 PSIL_SA2UL(0x4002, 0),
57 PSIL_SA2UL(0x4003, 0),
59 PSIL_ETHERNET(0x4100),
60 PSIL_ETHERNET(0x4101),
61 PSIL_ETHERNET(0x4102),
62 PSIL_ETHERNET(0x4103),
64 PSIL_ETHERNET(0x4200),
65 PSIL_ETHERNET(0x4201),
[all …]
H A Dk3-psil-j721s2.c63 PSIL_PDMA_MCASP(0x4400),
64 PSIL_PDMA_MCASP(0x4401),
65 PSIL_PDMA_MCASP(0x4402),
66 PSIL_PDMA_MCASP(0x4403),
67 PSIL_PDMA_MCASP(0x4404),
69 PSIL_PDMA_XY_PKT(0x4600),
70 PSIL_PDMA_XY_PKT(0x4601),
71 PSIL_PDMA_XY_PKT(0x4602),
72 PSIL_PDMA_XY_PKT(0x4603),
73 PSIL_PDMA_XY_PKT(0x4604),
[all …]
H A Dk3-psil-j7200.c64 PSIL_PDMA_MCASP(0x4400),
65 PSIL_PDMA_MCASP(0x4401),
66 PSIL_PDMA_MCASP(0x4402),
68 PSIL_PDMA_XY_PKT(0x4600),
69 PSIL_PDMA_XY_PKT(0x4601),
70 PSIL_PDMA_XY_PKT(0x4602),
71 PSIL_PDMA_XY_PKT(0x4603),
72 PSIL_PDMA_XY_PKT(0x4604),
73 PSIL_PDMA_XY_PKT(0x4605),
74 PSIL_PDMA_XY_PKT(0x4606),
[all …]
H A Dk3-psil-j784s4.c71 PSIL_PDMA_MCASP(0x4400),
72 PSIL_PDMA_MCASP(0x4401),
73 PSIL_PDMA_MCASP(0x4402),
74 PSIL_PDMA_MCASP(0x4403),
75 PSIL_PDMA_MCASP(0x4404),
77 PSIL_PDMA_XY_PKT(0x4600),
78 PSIL_PDMA_XY_PKT(0x4601),
79 PSIL_PDMA_XY_PKT(0x4602),
80 PSIL_PDMA_XY_PKT(0x4603),
81 PSIL_PDMA_XY_PKT(0x4604),
[all …]
H A Dk3-psil-j721e.c72 PSIL_SA2UL(0x4000, 0),
73 PSIL_SA2UL(0x4001, 0),
74 PSIL_SA2UL(0x4002, 0),
75 PSIL_SA2UL(0x4003, 0),
77 PSIL_ETHERNET(0x4100),
78 PSIL_ETHERNET(0x4101),
79 PSIL_ETHERNET(0x4102),
80 PSIL_ETHERNET(0x4103),
82 PSIL_ETHERNET(0x4200),
83 PSIL_ETHERNET(0x4201),
[all …]
/openbmc/linux/arch/arm/mach-s5pv210/
H A Dregs-clock.h12 #define S3C_ADDR_BASE 0xF6000000
14 #define S3C_VA_SYS S3C_ADDR(0x00100000)
18 #define S5P_APLL_LOCK S5P_CLKREG(0x00)
19 #define S5P_MPLL_LOCK S5P_CLKREG(0x08)
20 #define S5P_EPLL_LOCK S5P_CLKREG(0x10)
21 #define S5P_VPLL_LOCK S5P_CLKREG(0x20)
23 #define S5P_APLL_CON S5P_CLKREG(0x100)
24 #define S5P_MPLL_CON S5P_CLKREG(0x108)
25 #define S5P_EPLL_CON S5P_CLKREG(0x110)
26 #define S5P_EPLL_CON1 S5P_CLKREG(0x114)
[all …]
/openbmc/linux/sound/soc/intel/catpt/
H A Dregisters.h22 #define CATPT_SHIM_CS1 0x00
23 #define CATPT_SHIM_ISC 0x18
24 #define CATPT_SHIM_ISD 0x20
25 #define CATPT_SHIM_IMC 0x28
26 #define CATPT_SHIM_IMD 0x30
27 #define CATPT_SHIM_IPCC 0x38
28 #define CATPT_SHIM_IPCD 0x40
29 #define CATPT_SHIM_CLKCTL 0x78
30 #define CATPT_SHIM_CS2 0x80
31 #define CATPT_SHIM_LTRC 0xE0
[all …]
/openbmc/linux/include/linux/mtd/
H A Donenand_regs.h20 #define ONENAND_BOOTRAM ONENAND_MEMORY_MAP(0x0000)
21 #define ONENAND_DATARAM ONENAND_MEMORY_MAP(0x0200)
22 #define ONENAND_SPARERAM ONENAND_MEMORY_MAP(0x8010)
27 #define ONENAND_REG_MANUFACTURER_ID ONENAND_MEMORY_MAP(0xF000)
28 #define ONENAND_REG_DEVICE_ID ONENAND_MEMORY_MAP(0xF001)
29 #define ONENAND_REG_VERSION_ID ONENAND_MEMORY_MAP(0xF002)
30 #define ONENAND_REG_DATA_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF003)
31 #define ONENAND_REG_BOOT_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF004)
32 #define ONENAND_REG_NUM_BUFFERS ONENAND_MEMORY_MAP(0xF005)
33 #define ONENAND_REG_TECHNOLOGY ONENAND_MEMORY_MAP(0xF006)
[all …]
/openbmc/u-boot/include/linux/mtd/
H A Donenand_regs.h23 #define ONENAND_BOOTRAM ONENAND_MEMORY_MAP(0x0000)
24 #define ONENAND_DATARAM ONENAND_MEMORY_MAP(0x0200)
25 #define ONENAND_SPARERAM ONENAND_MEMORY_MAP(0x8010)
30 #define ONENAND_REG_MANUFACTURER_ID ONENAND_MEMORY_MAP(0xF000)
31 #define ONENAND_REG_DEVICE_ID ONENAND_MEMORY_MAP(0xF001)
32 #define ONENAND_REG_VERSION_ID ONENAND_MEMORY_MAP(0xF002)
33 #define ONENAND_REG_DATA_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF003)
34 #define ONENAND_REG_BOOT_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF004)
35 #define ONENAND_REG_NUM_BUFFERS ONENAND_MEMORY_MAP(0xF005)
36 #define ONENAND_REG_TECHNOLOGY ONENAND_MEMORY_MAP(0xF006)
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/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-devices-platform-stratix10-rsu3 What: /sys/devices/platform/stratix10-rsu.0/current_image
10 What: /sys/devices/platform/stratix10-rsu.0/fail_image
17 What: /sys/devices/platform/stratix10-rsu.0/state
26 b[15:0]
27 Currently used only when major error is 0xF006
34 0xF001 bitstream error
35 0xF002 hardware access failure
36 0xF003 bitstream corruption
37 0xF004 internal error
38 0xF005 device error
[all …]
/openbmc/linux/drivers/tty/vt/
H A Ddefkeymap.c_shipped10 0xf200, 0xf01b, 0xf031, 0xf032, 0xf033, 0xf034, 0xf035, 0xf036,
11 0xf037, 0xf038, 0xf039, 0xf030, 0xf02d, 0xf03d, 0xf07f, 0xf009,
12 0xfb71, 0xfb77, 0xfb65, 0xfb72, 0xfb74, 0xfb79, 0xfb75, 0xfb69,
13 0xfb6f, 0xfb70, 0xf05b, 0xf05d, 0xf201, 0xf702, 0xfb61, 0xfb73,
14 0xfb64, 0xfb66, 0xfb67, 0xfb68, 0xfb6a, 0xfb6b, 0xfb6c, 0xf03b,
15 0xf027, 0xf060, 0xf700, 0xf05c, 0xfb7a, 0xfb78, 0xfb63, 0xfb76,
16 0xfb62, 0xfb6e, 0xfb6d, 0xf02c, 0xf02e, 0xf02f, 0xf700, 0xf30c,
17 0xf703, 0xf020, 0xf207, 0xf100, 0xf101, 0xf102, 0xf103, 0xf104,
18 0xf105, 0xf106, 0xf107, 0xf108, 0xf109, 0xf208, 0xf209, 0xf307,
19 0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dti,k3-am654-cpsw-nuss.yaml19 The internal Communications Port Programming Interface (CPPI5) (Host port 0).
20 Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
27 Support for Audio/Video Bridging (P802.1Qav/D6.0)
31 IEEE P902.3br/D2.0 Interspersing Express Traffic
113 const: 0
169 "^mdio@[0-9a-f]+$":
176 "^cpts@[0-9a-f]+":
252 reg = <0x0 0x46000000 0x0 0x200000>;
254 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
260 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
[all …]
/openbmc/linux/drivers/s390/char/
H A Ddefkeymap.c15 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000,
16 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000,
17 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000,
18 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000,
19 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000,
20 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000,
21 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000,
22 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000,
23 0xf020, 0xf000, 0xf0e2, 0xf0e4, 0xf0e0, 0xf0e1, 0xf0e3, 0xf0e5,
24 0xf0e7, 0xf0f1, 0xf0a2, 0xf02e, 0xf03c, 0xf028, 0xf02b, 0xf07c,
[all …]
/openbmc/u-boot/drivers/video/
H A Dformike.c12 #define TAG_READ 0x80
13 #define TAG_WRITE 0x00
15 #define TAG_DATA 0x40
16 #define TAG_COMMAND 0x00
18 #define TAG_ADDR_H 0x20
19 #define TAG_ADDR_L 0x00
28 buf[0] = tag; in spi_write_tag_val()
30 buf[0] = val; in spi_write_tag_val()
52 (addr & 0xff00) >> 8); in spi_write_com()
54 (addr & 0x00ff) >> 0); in spi_write_com()
[all …]
H A Dmvebu_lcd.c16 #define MVEBU_LCD_WIN_CONTROL(w) (0xf000 + ((w) << 4))
17 #define MVEBU_LCD_WIN_BASE(w) (0xf004 + ((w) << 4))
18 #define MVEBU_LCD_WIN_REMAP(w) (0xf00c + ((w) << 4))
20 #define MVEBU_LCD_CFG_DMA_START_ADDR_0 0x00cc
21 #define MVEBU_LCD_CFG_DMA_START_ADDR_1 0x00dc
23 #define MVEBU_LCD_CFG_GRA_START_ADDR0 0x00f4
24 #define MVEBU_LCD_CFG_GRA_START_ADDR1 0x00f8
25 #define MVEBU_LCD_CFG_GRA_PITCH 0x00fc
26 #define MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN 0x0100
27 #define MVEBU_LCD_SPU_GRA_HPXL_VLN 0x0104
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-mcu.dtsi11 reg = <0x0 0x40f00000 0x0 0x20000>;
14 ranges = <0x0 0x0 0x40f00000 0x20000>;
18 reg = <0x4040 0x4>;
26 reg = <0x0 0x40f04200 0x0 0x10>;
29 pinctrl-single,function-mask = <0x00000101>;
35 reg = <0x0 0x40f04280 0x0 0x8>;
38 pinctrl-single,function-mask = <0x00000003>;
43 reg = <0x00 0x40a00000 0x00 0x100>;
53 reg = <0x00 0x41c00000 0x00 0x80000>;
54 ranges = <0x0 0x00 0x41c00000 0x80000>;
[all …]
H A Dk3-j721s2-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
39 reg = <0x00 0x43000014 0x00 0x4>;
46 reg = <0x00 0x43600000 0x00 0x10000>,
47 <0x00 0x44880000 0x00 0x20000>,
48 <0x00 0x44860000 0x00 0x20000>;
59 reg = <0x00 0x41c00000 0x00 0x100000>;
60 ranges = <0x00 0x00 0x41c00000 0x100000>;
67 /* Proxy 0 addressing */
68 reg = <0x00 0x4301c000 0x00 0x034>;
71 pinctrl-single,function-mask = <0xffffffff>;
[all …]
H A Dk3-j7200-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
40 reg = <0x00 0x40400000 0x00 0x400>;
53 reg = <0x00 0x40410000 0x00 0x400>;
57 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
66 reg = <0x00 0x40420000 0x00 0x400>;
79 reg = <0x00 0x40430000 0x00 0x400>;
83 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
92 reg = <0x00 0x40440000 0x00 0x400>;
105 reg = <0x00 0x40450000 0x00 0x400>;
109 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Dgcc-sdx55.c33 { 249600000, 2000000000, 0 },
37 .offset = 0x0,
42 .enable_reg = 0x6d000,
43 .enable_mask = BIT(0),
56 { 0x0, 1 },
57 { 0x1, 2 },
58 { 0x3, 4 },
59 { 0x7, 8 },
64 .offset = 0x0,
81 .offset = 0x76000,
[all …]

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