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/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Datmel-can.txt13 reg = <0xf000c000 0x300>;
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dsama5d3_can.dtsi36 reg = <0xf000c000 0x300>;
39 pinctrl-0 = <&pinctrl_can0_rx_tx>;
47 reg = <0xf8010000 0x300>;
50 pinctrl-0 = <&pinctrl_can1_rx_tx>;
H A Dat91sam9x5.dtsi44 #size-cells = <0>;
46 cpu@0 {
49 reg = <0>;
55 reg = <0x20000000 0x10000000>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
73 #clock-cells = <0>;
80 reg = <0x00300000 0x8000>;
[all …]
H A Dsama5d2.dtsi29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
41 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
46 reg = <0x740000 0x1000>;
62 reg = <0x73c000 0x1000>;
78 reg = <0x20000000 0x20000000>;
84 #clock-cells = <0>;
85 clock-frequency = <0>;
90 #clock-cells = <0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dnuvoton,npcm750-adc.yaml61 reg = <0xf000c000 0x8>;
62 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
/openbmc/u-boot/arch/arm/dts/
H A Dsama5d3_can.dtsi38 #clock-cells = <0>;
40 atmel,clk-output-range = <0 66000000>;
44 #clock-cells = <0>;
46 atmel,clk-output-range = <0 66000000>;
53 reg = <0xf000c000 0x300>;
56 pinctrl-0 = <&pinctrl_can0_rx_tx>;
64 reg = <0xf8010000 0x300>;
67 pinctrl-0 = <&pinctrl_can1_rx_tx>;
H A Dat91sam9x5.dtsi51 reg = <0x20000000 0x10000000>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
63 #clock-cells = <0>;
64 clock-frequency = <0>;
69 #clock-cells = <0>;
76 reg = <0x00300000 0x8000>;
97 reg = <0xfffff000 0x200>;
103 reg = <0xffffe800 0x200>;
110 reg = <0xfffffc00 0x200>;
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91sam9x5.h17 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
23 #define ATMEL_ID_USART0 5 /* USART 0 */
27 #define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */
30 #define ATMEL_ID_HSMCI0 12 /* High Speed Multimedia Card Interface 0 */
31 #define ATMEL_ID_SPI0 13 /* Serial Peripheral Interface 0 */
33 #define ATMEL_ID_UART0 15 /* UART 0 */
35 #define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
38 #define ATMEL_ID_DMAC0 20 /* DMA Controller 0 */
53 #define ATMEL_BASE_SPI0 0xf0000000
54 #define ATMEL_BASE_SPI1 0xf0004000
[all …]
H A Dsama5d3.h18 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
30 #define ATMEL_ID_USART0 12 /* USART 0 */
36 #define ATMEL_ID_TWI0 18 /* Two-Wire Interface 0 */
39 #define ATMEL_ID_MCI0 21 /* High Speed Multimedia Card Interface 0 */
42 #define ATMEL_ID_SPI0 24 /* Serial Peripheral Interface 0 */
56 #define ATMEL_ID_SSC0 38 /* Synchronous Serial Controller 0 */
70 #define ARCH_ID_SAMA5D3 0x8a5c07c0
71 #define ARCH_EXID_SAMA5D31 0x00444300
72 #define ARCH_EXID_SAMA5D33 0x00414300
73 #define ARCH_EXID_SAMA5D34 0x00414301
[all …]
H A Dsama5d4.h15 #define ATMEL_ID_FIQ 0 /* FIQ Interrupt */
21 #define ATMEL_ID_USART0 6 /* USART 0 */
23 #define ATMEL_ID_DMA0 8 /* DMA Controller 0 */
40 #define ATMEL_ID_UART0 27 /* UART 0 */
45 #define ATMEL_ID_TWI0 32 /* Two-Wire Interface 0 */
48 #define ATMEL_ID_MCI0 35 /* High Speed Multimedia Card Interface 0 */
50 #define ATMEL_ID_SPI0 37 /* Serial Peripheral Interface 0 */
53 #define ATMEL_ID_TC0 40 /* Timer Counter 0 (ch. 0, 1, 2) */
61 #define ATMEL_ID_SSC0 48 /* Synchronous Serial Controller 0 */
67 #define ATMEL_ID_GMAC0 54 /* Ethernet MAC 0 */
[all …]
H A Dsama5d2.h15 #define ATMEL_ID_FIQ 0 /* FIQ Interrupt ID */
21 #define ATMEL_ID_XDMAC0 6 /* DMA Controller 0 */
44 #define ATMEL_ID_TWIHS0 29 /* Two-wire Interface 0 */
46 #define ATMEL_ID_SDMMC0 31 /* Secure Data Memory Card Controller 0 */
48 #define ATMEL_ID_SPI0 33 /* Serial Peripheral Interface 0 */
50 #define ATMEL_ID_TC0 35 /* Timer Counter 0 (ch.0,1,2) */
53 #define ATMEL_ID_PWM 38 /* PWMController0 (ch. 0,1,2,3) */
58 #define ATMEL_ID_SSC0 43 /* Serial Synchronous Controller 0 */
69 #define ATMEL_ID_I2SC0 54 /* Inter-IC Sound Controller 0 */
71 #define ATMEL_ID_CAN0_INT0 56 /* MCAN 0 Interrupt0 */
[all …]
/openbmc/qemu/tests/qtest/
H A Dnpcm7xx_adc-test.c25 #define CON_OFFSET 0x0
26 #define DATA_OFFSET 0x4
38 #define FUSE_ARRAY_BA 0xf018a000
39 #define FCTL_OFFSET 0x14
40 #define FST_OFFSET 0x0
41 #define FADDR_OFFSET 0x4
42 #define FDATA_OFFSET 0x8
44 #define FUSE_READ 0x2
57 #define FDATA_MASK 0xff
86 static const uint32_t div_list[] = {0, 1, 3, 7, 15};
[all …]
/openbmc/qemu/hw/arm/
H A Dnpcm7xx.c36 #define NPCM7XX_MMIO_BA (0x80000000)
37 #define NPCM7XX_MMIO_SZ (0x7ffd0000)
40 #define NPCM7XX_OTP1_BA (0xf0189000)
41 #define NPCM7XX_OTP2_BA (0xf018a000)
44 #define NPCM7XX_L2C_BA (0xf03fc000)
45 #define NPCM7XX_CPUP_BA (0xf03fe000)
46 #define NPCM7XX_GCR_BA (0xf0800000)
47 #define NPCM7XX_CLK_BA (0xf0801000)
48 #define NPCM7XX_MC_BA (0xf0824000)
49 #define NPCM7XX_RNG_BA (0xf000b000)
[all …]
/openbmc/linux/arch/arm/probes/
H A Ddecode-thumb.c20 DECODE_REJECT (0xfe4f0000, 0xe80f0000),
24 DECODE_REJECT (0xffc00000, 0xe8000000),
27 DECODE_REJECT (0xffc00000, 0xe9800000),
30 DECODE_REJECT (0xfe508000, 0xe8008000),
32 DECODE_REJECT (0xfe50c000, 0xe810c000),
34 DECODE_REJECT (0xfe402000, 0xe8002000),
40 DECODE_CUSTOM (0xfe400000, 0xe8000000, PROBES_T32_LDMSTM),
50 DECODE_OR (0xff600000, 0xe8600000),
53 DECODE_EMULATEX (0xff400000, 0xe9400000, PROBES_T32_LDRDSTRD,
54 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)),
[all …]
/openbmc/linux/arch/arm/
H A DKconfig.debug149 0x80000000 | 0xf0000000 | UART0
150 0x80004000 | 0xf0004000 | UART1
151 0x80008000 | 0xf0008000 | UART2
152 0x8000c000 | 0xf000c000 | UART3
153 0x80010000 | 0xf0010000 | UART4
154 0x80014000 | 0xf0014000 | UART5
155 0x80018000 | 0xf0018000 | UART6
156 0x8001c000 | 0xf001c000 | UART7
157 0x80020000 | 0xf0020000 | UART8
158 0x80024000 | 0xf0024000 | UART9
[all …]