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Searched +full:0 +full:xf0001000 (Results 1 – 10 of 10) sorted by relevance

/openbmc/u-boot/board/synopsys/emsdp/
H A DREADME78 need to enable writes into "ROM" by writing 1 to 0xf0001000.
82 mdb -dll=opxdarc.so -OK -preloadexec="eval *(int*)0xf0001000=0" u-boot
H A Demsdp.c14 #define ARC_PERIPHERAL_BASE 0xF0000000
16 #define CGU_ARC_FMEAS_ARC (void *)(ARC_PERIPHERAL_BASE + 0x84)
19 #define CGU_ARC_FMEAS_ARC_CNT_MASK GENMASK(14, 0)
20 #define CGU_ARC_FMEAS_ARC_RCNT_OFFSET 0
23 #define SDIO_BASE (void *)(ARC_PERIPHERAL_BASE + 0x10000)
48 return 0; in mach_cpu_init()
61 memset(host, 0, sizeof(struct dwmci_host)); in board_mmc_init()
65 host->dev_index = 0; in board_mmc_init()
70 return 0; in board_mmc_init()
80 #define CREG_BASE 0xF0001000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Darm,arch_timer_mmio.yaml63 '^frame@[0-9a-z]*$':
70 minimum: 0
104 ranges = <0 0xf0001000 0x1000>;
105 reg = <0xf0000000 0x1000>;
108 frame@0 {
109 frame-number = <0>;
110 interrupts = <0 13 0x8>,
111 <0 14 0x8>;
112 reg = <0x0000 0x1000>,
113 <0x1000 0x1000>;
[all …]
/openbmc/linux/arch/arc/plat-axs10x/
H A Daxs10x.c16 #define AXS_MB_CGU 0xE0010000
17 #define AXS_MB_CREG 0xE0011000
19 #define CREG_MB_IRQ_MUX (AXS_MB_CREG + 0x214)
20 #define CREG_MB_SW_RESET (AXS_MB_CREG + 0x220)
21 #define CREG_MB_VER (AXS_MB_CREG + 0x230)
22 #define CREG_MB_CONFIG (AXS_MB_CREG + 0x234)
24 #define AXC001_CREG 0xF0001000
25 #define AXC001_GPIO_INTC 0xF0003000
61 #define GPIO_INTEN (AXC001_GPIO_INTC + 0x30) in axs10x_enable_gpio_intc_wire()
62 #define GPIO_INTMASK (AXC001_GPIO_INTC + 0x34) in axs10x_enable_gpio_intc_wire()
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/openbmc/qemu/tests/avocado/
H A Dboot_linux_console.py31 return 1 if x == 0 else 2**(x - 1).bit_length()
49 KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
204 '3 packets transmitted, 3 packets received, 0% packet loss')
214 'linux-image-4.19.0-6-armmp_4.19.67-2+deb10u1_armhf.deb')
218 '/boot/vmlinuz-4.19.0-6-armmp')
219 dtb_path = '/usr/lib/linux-image-4.19.0-6-armmp/exynos4210-smdkv310.dtb'
232 'earlycon=exynos4210,0x13800000 earlyprintk ' +
323 '-device', 'ide-hd,bus=ide.0,drive=disk0',
398 '20200711-gsj-qemu-0/obmc-phosphor-image-gsj.static.mtd.gz')
406 drive_args = 'file=' + image_path + ',if=mtd,bus=0,unit=0'
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/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dmmp3.dtsi16 #size-cells = <0>;
19 cpu@0 {
23 reg = <0>;
45 reg = <0xd4200000 0x00200000>;
52 reg = <0xd4282000 0x1000>,
53 <0xd4284000 0x100>;
62 reg = <0x150 0x4>, <0x168 0x4>;
72 reg = <0x154 0x4>, <0x16c 0x4>;
82 reg = <0x1bc 0x4>, <0x1a4 0x4>;
92 reg = <0x1c0 0x4>, <0x1a8 0x4>;
[all …]
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7779.dtsi22 #size-cells = <0>;
24 cpu@0 {
27 reg = <0>;
67 reg = <0xf0001000 0x1000>,
68 <0xf0000100 0x100>;
73 reg = <0xf0000200 0x100>;
81 reg = <0xf0000600 0x20>;
89 reg = <0xffc40000 0x2c>;
93 gpio-ranges = <&pfc 0 0 32>;
100 reg = <0xffc41000 0x2c>;
[all …]
H A Dsh73a0.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0>;
44 reg = <0xf0000200 0x100>;
51 reg = <0xf0000600 0x20>;
60 reg = <0xf0001000 0x1000>,
61 <0xf0000100 0x100>;
66 reg = <0xf0100000 0x1000>;
78 reg = <0xfb400000 0x400>;
87 reg = <0xfe400000 0x400>;
[all …]
/openbmc/qemu/hw/arm/
H A Dnpcm7xx.c36 #define NPCM7XX_MMIO_BA (0x80000000)
37 #define NPCM7XX_MMIO_SZ (0x7ffd0000)
40 #define NPCM7XX_OTP1_BA (0xf0189000)
41 #define NPCM7XX_OTP2_BA (0xf018a000)
44 #define NPCM7XX_L2C_BA (0xf03fc000)
45 #define NPCM7XX_CPUP_BA (0xf03fe000)
46 #define NPCM7XX_GCR_BA (0xf0800000)
47 #define NPCM7XX_CLK_BA (0xf0801000)
48 #define NPCM7XX_MC_BA (0xf0824000)
49 #define NPCM7XX_RNG_BA (0xf000b000)
[all …]
/openbmc/qemu/hw/i2c/
H A Daspeed_i2c.c120 value = extract64(bus->dma_dram_offset, 0, 32); in aspeed_i2c_bus_old_read()
131 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); in aspeed_i2c_bus_old_read()
167 value = extract64(bus->dma_dram_offset, 0, 32); in aspeed_i2c_bus_new_read()
186 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); in aspeed_i2c_bus_new_read()
241 return 0; in aspeed_i2c_dma_read()
257 for (i = 0; i < pool_tx_count; i++) { in aspeed_i2c_bus_send()
267 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_BUFF_EN, 0); in aspeed_i2c_bus_send()
271 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, 0); in aspeed_i2c_bus_send()
289 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_DMA_EN, 0); in aspeed_i2c_bus_send()
291 trace_aspeed_i2c_bus_send("BYTE", 0, 1, in aspeed_i2c_bus_send()
[all …]