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/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dmarvell,berlin2-reset.yaml32 reg = <0xea0000 0x400>;
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dsyna.txt57 reg = <0xf7dd0000 0x10000>;
91 reg = <0xea0000 0x400>;
98 reg = <0xd000 0x100>;
/openbmc/linux/arch/arm/boot/dts/synaptics/
H A Dberlin2.dtsi28 #size-cells = <0>;
31 cpu@0 {
35 reg = <0>;
68 #clock-cells = <0>;
78 ranges = <0 0xf7000000 0x1000000>;
82 reg = <0xab0000 0x200>;
91 reg = <0xab0800 0x200>;
100 reg = <0xab1000 0x200>;
104 pinctrl-0 = <&emmc_pmux>;
111 reg = <0xac0000 0x1000>;
[all …]
H A Dberlin2cd.dtsi27 #size-cells = <0>;
29 cpu: cpu@0 {
33 reg = <0>;
53 #clock-cells = <0>;
63 ranges = <0 0xf7000000 0x1000000>;
67 reg = <0xab0000 0x200>;
76 reg = <0xac0000 0x1000>;
83 reg = <0xad0000 0x100>;
88 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
95 reg = <0xad0200 0x20>;
[all …]
H A Dberlin2q.dtsi22 #size-cells = <0>;
25 cpu0: cpu@0 {
29 reg = <0>;
113 #clock-cells = <0>;
122 ranges = <0 0xf7000000 0x1000000>;
127 reg = <0xab0000 0x200>;
136 reg = <0xab0800 0x200>;
145 reg = <0xab1000 0x200>;
154 reg = <0xac0000 0x1000>;
163 reg = <0xad0000 0x58>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch3.h12 #define CONFIG_SYS_IMMR 0x01000000
13 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
14 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
15 #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
16 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
17 #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
19 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
21 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
23 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
24 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
[all …]
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dxtensa-modules.c.inc31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
[all …]
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dxtensa-modules.c.inc31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "MMID", 89, 0 },
36 { "DDR", 104, 0 },
37 { "176", 176, 0 },
38 { "208", 208, 0 },
39 { "INTERRUPT", 226, 0 },
40 { "INTCLEAR", 227, 0 },
[all …]