Searched +full:0 +full:xe0007000 (Results 1 – 6 of 6) sorted by relevance
28 interrupts = <0 49 4>;30 is-decoded-cs = <0>;31 reg = <0xe0007000 0x1000>;
49 enum: [ 0, 1 ]50 default: 074 interrupts = <0 49 4>;76 is-decoded-cs = <0>;77 reg = <0xe0007000 0x1000>;
15 * but many hardware register are accessible at 0xb9000000 in16 * instead of 0xe0000000.19 #define JAZZ_LOCAL_IO_SPACE 0xe000000024 * 0xf0000000 - Rev125 * 0xf0000001 - Rev226 * 0xf0000002 - Rev328 #define PICA_ASIC_REVISION 0xe000000843 * --------- . (0)45 #define PICA_LED 0xe000f00054 #define LED_DOT 0x01[all …]
16 #size-cells = <0>;18 cpu0: cpu@0 {21 reg = <0>;50 interrupts = <0 5 4>, <0 6 4>;52 reg = <0xf8891000 0x1000>,53 <0xf8893000 0x1000>;75 reg = <0xf8007100 0x20>;76 interrupts = <0 7 4>;86 reg = <0xe0008000 0x1000>;87 interrupts = <0 28 4>;[all …]
13 #size-cells = <0>;15 cpu0: cpu@0 {18 reg = <0>;47 interrupts = <0 5 4>, <0 6 4>;49 reg = <0xf8891000 0x1000>,50 <0xf8893000 0x1000>;69 #size-cells = <0>;72 port@0 {73 reg = <0>;104 reg = <0xf8007100 0x20>;[all …]
59 #define MPCORE_PERIPHBASE 0xF8F0000060 #define ZYNQ_BOARD_MIDR 0x413FC09066 #define BOARD_SETUP_ADDR 0x10068 #define SLCR_LOCK_OFFSET 0x00469 #define SLCR_UNLOCK_OFFSET 0x00870 #define SLCR_ARM_PLL_OFFSET 0x10072 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d73 #define SLCR_XILINX_LOCK_KEY 0x767b75 #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */77 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \[all …]