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/openbmc/qemu/tests/qemu-iotests/
H A D04625 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
60 local pattern=0
61 local cur_sec=0
63 for ((i=0;i<=$((sectors - 1));i++)); do
71 backing_io 0 32 write | $QEMU_IO "$TEST_IMG" | _filter_qemu_io
84 aio_write -P 10 0x18000 0x2000
87 aio_write -P 11 0x12000 0x2000
88 aio_write -P 12 0x1c000 0x2000
98 aio_write -P 20 0x28000 0x2000
[all …]
H A D07725 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
57 aio_write -P 10 0x200 0x200
62 off=0x1000
66 aio_write -P 10 $((off + 0x200)) 0x200
68 aio_write -P 11 $((off + 0x400)) 0x200
73 off=$((off + 0x1000))
79 aio_write -P 10 0x5000 0x200
81 aio_write -P 11 0x5200 0x200
82 aio_write -P 12 0x5400 0x200
[all …]
/openbmc/linux/include/linux/mfd/wm8350/
H A Dcomparator.h15 #define WM8350_DIGITISER_CONTROL_1 0x90
16 #define WM8350_DIGITISER_CONTROL_2 0x91
17 #define WM8350_AUX1_READBACK 0x98
18 #define WM8350_AUX2_READBACK 0x99
19 #define WM8350_AUX3_READBACK 0x9A
20 #define WM8350_AUX4_READBACK 0x9B
21 #define WM8350_CHIP_TEMP_READBACK 0x9F
22 #define WM8350_GENERIC_COMPARATOR_CONTROL 0xA3
23 #define WM8350_GENERIC_COMPARATOR_1 0xA4
24 #define WM8350_GENERIC_COMPARATOR_2 0xA5
[all …]
/openbmc/linux/include/linux/mfd/wm831x/
H A Dregulator.h14 * R16462 (0x404E) - Current Sink 1
16 #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
17 #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
20 #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
21 #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
24 #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
25 #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
28 #define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
31 #define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */
34 #define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */
[all …]
H A Dauxadc.h16 * R16429 (0x402D) - AuxADC Data
18 #define WM831X_AUX_DATA_SRC_MASK 0xF000 /* AUX_DATA_SRC - [15:12] */
21 #define WM831X_AUX_DATA_MASK 0x0FFF /* AUX_DATA - [11:0] */
22 #define WM831X_AUX_DATA_SHIFT 0 /* AUX_DATA - [11:0] */
23 #define WM831X_AUX_DATA_WIDTH 12 /* AUX_DATA - [11:0] */
26 * R16430 (0x402E) - AuxADC Control
28 #define WM831X_AUX_ENA 0x8000 /* AUX_ENA */
29 #define WM831X_AUX_ENA_MASK 0x8000 /* AUX_ENA */
32 #define WM831X_AUX_CVT_ENA 0x4000 /* AUX_CVT_ENA */
33 #define WM831X_AUX_CVT_ENA_MASK 0x4000 /* AUX_CVT_ENA */
[all …]
/openbmc/u-boot/drivers/dma/
H A DMCD_tasksInit.c18 /* Task 0 */
27 MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ in MCD_startDmaChainNoEu()
28 MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ in MCD_startDmaChainNoEu()
30 MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ in MCD_startDmaChainNoEu()
31 MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */ in MCD_startDmaChainNoEu()
32 MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */ in MCD_startDmaChainNoEu()
33 MCD_SET_VAR(taskChan, 3, (u32) 0x00000000); /* var[3] */ in MCD_startDmaChainNoEu()
34 MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */ in MCD_startDmaChainNoEu()
35 MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */ in MCD_startDmaChainNoEu()
36 MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */ in MCD_startDmaChainNoEu()
[all …]
/openbmc/linux/drivers/video/fbdev/sis/
H A Dsis_accel.h39 #define PATREGSIZE 384 /* Pattern register size. 384 bytes @ 0x8300 */
40 #define BR(x) (0x8200 | (x) << 2)
41 #define PBR(x) (0x8300 | (x) << 2)
44 #define BITBLT 0x00000000 /* Blit */
45 #define COLOREXP 0x00000001 /* Color expand */
46 #define ENCOLOREXP 0x00000002 /* Enhanced color expand */
47 #define MULTIPLE_SCANLINE 0x00000003 /* ? */
48 #define LINE 0x00000004 /* Draw line */
49 #define TRAPAZOID_FILL 0x00000005 /* Fill trapezoid */
50 #define TRANSPARENT_BITBLT 0x00000006 /* Transparent Blit */
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dtqm8540.dts29 #size-cells = <0>;
31 PowerPC,8540@0 {
33 reg = <0>;
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
47 reg = <0x00000000 0x10000000>;
54 ranges = <0x0 0xe0000000 0x100000>;
55 bus-frequency = <0>;
58 ecm-law@0 {
[all …]
H A Dtqm8541.dts28 #size-cells = <0>;
30 PowerPC,8541@0 {
32 reg = <0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
46 reg = <0x00000000 0x10000000>;
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
[all …]
H A Dtqm8555.dts28 #size-cells = <0>;
30 PowerPC,8555@0 {
32 reg = <0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
46 reg = <0x00000000 0x10000000>;
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
[all …]
H A Dtqm8560.dts30 #size-cells = <0>;
32 PowerPC,8560@0 {
34 reg = <0>;
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
48 reg = <0x00000000 0x10000000>;
55 ranges = <0x0 0xe0000000 0x100000>;
56 bus-frequency = <0>;
59 ecm-law@0 {
[all …]
H A Dtqm8548.dts31 #size-cells = <0>;
33 PowerPC,8548@0 {
35 reg = <0>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
46 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
59 reg = <0x0 0x1000>;
[all …]
H A Dtqm8548-bigflash.dts31 #size-cells = <0>;
33 PowerPC,8548@0 {
35 reg = <0>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
46 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x0 0xa0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
59 reg = <0x0 0x1000>;
[all …]
H A Dmpc8379_rdb.dts25 #size-cells = <0>;
27 PowerPC,8379@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>;
35 bus-frequency = <0>;
36 clock-frequency = <0>;
42 reg = <0x00000000 0x10000000>; // 256MB at 0
49 reg = <0xe0005000 0x1000>;
50 interrupts = <77 0x8>;
56 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
H A Dmpc8377_rdb.dts27 #size-cells = <0>;
29 PowerPC,8377@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x00000000 0x10000000>; // 256MB at 0
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
58 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
H A Dmpc8378_rdb.dts27 #size-cells = <0>;
29 PowerPC,8378@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x00000000 0x10000000>; // 256MB at 0
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
58 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
/openbmc/linux/drivers/mfd/
H A Dcs47l85-tables.c18 { 0x80, 0x0003 },
19 { 0x213, 0x03E4 },
20 { 0x177, 0x0281 },
21 { 0x197, 0x0281 },
22 { 0x1B7, 0x0281 },
23 { 0x4B1, 0x010A },
24 { 0x4CF, 0x0933 },
25 { 0x36C, 0x011B },
26 { 0x4B8, 0x1120 },
27 { 0x4A0, 0x3280 },
[all …]
/openbmc/linux/sound/pci/hda/
H A Dca0132_regs.h12 #define DSP_CHIP_OFFSET 0x100000
13 #define DSP_DBGCNTL_MODULE_OFFSET 0xE30
17 #define DSP_DBGCNTL_EXEC_LOBIT 0x0
18 #define DSP_DBGCNTL_EXEC_HIBIT 0x3
19 #define DSP_DBGCNTL_EXEC_MASK 0xF
21 #define DSP_DBGCNTL_SS_LOBIT 0x4
22 #define DSP_DBGCNTL_SS_HIBIT 0x7
23 #define DSP_DBGCNTL_SS_MASK 0xF0
25 #define DSP_DBGCNTL_STATE_LOBIT 0xA
26 #define DSP_DBGCNTL_STATE_HIBIT 0xD
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dreg_wow.h20 #define AR_WOW_PATTERN 0x825C
21 #define AR_WOW_COUNT 0x8260
22 #define AR_WOW_BCN_EN 0x8270
23 #define AR_WOW_BCN_TIMO 0x8274
24 #define AR_WOW_KEEP_ALIVE_TIMO 0x8278
25 #define AR_WOW_KEEP_ALIVE 0x827c
26 #define AR_WOW_KEEP_ALIVE_DELAY 0x8288
27 #define AR_WOW_PATTERN_MATCH 0x828c
31 * bit 31:24 pattern 0 length
34 * bit 7:0 pattern 3 length
[all …]
/openbmc/linux/drivers/thermal/
H A Duniphier_thermal.c23 #define PVTCTLEN 0x0000
24 #define PVTCTLEN_EN BIT(0)
26 #define PVTCTLMODE 0x0004
27 #define PVTCTLMODE_MASK 0xf
28 #define PVTCTLMODE_TEMPMON 0x5
30 #define EMONREPEAT 0x0040
32 #define EMONREPEAT_PERIOD GENMASK(3, 0)
33 #define EMONREPEAT_PERIOD_1000000 0x9
39 #define PVTCTLSEL 0x0900
40 #define PVTCTLSEL_MASK GENMASK(2, 0)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/nuvoton/
H A Dnuvoton,gfxi.yaml38 reg = <0xe000 0x100>;
/openbmc/linux/arch/csky/kernel/
H A Djump_label.c10 #define NOP32_HI 0xc400
11 #define NOP32_LO 0x4820
12 #define BSR_LINK 0xe000
19 int ret = 0; in arch_jump_label_transform()
29 insn[0] = BSR_LINK | in arch_jump_label_transform()
30 ((uint16_t)((unsigned long) offset >> 16) & 0x3ff); in arch_jump_label_transform()
31 insn[1] = (uint16_t)((unsigned long) offset & 0xffff); in arch_jump_label_transform()
33 insn[0] = NOP32_HI; in arch_jump_label_transform()
/openbmc/u-boot/arch/x86/dts/
H A Dqemu-x86_i440fx.dts22 silent_console = <0>;
31 #size-cells = <0>;
34 cpu@0 {
38 reg = <0>;
39 intel,apic-id = <0>;
52 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
53 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
54 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
56 pch@1,0 {
57 reg = <0x00000800 0 0 0 0>;
[all …]
/openbmc/qemu/linux-user/include/host/riscv/
H A Dhost-signal.h40 uint16_t insn = pinsn[0]; in host_signal_write()
43 switch (insn & 0xe003) { in host_signal_write()
44 case 0xa000: /* c.fsd */ in host_signal_write()
45 case 0xc000: /* c.sw */ in host_signal_write()
46 case 0xe000: /* c.sd (rv64) / c.fsw (rv32) */ in host_signal_write()
47 case 0xa002: /* c.fsdsp */ in host_signal_write()
48 case 0xc002: /* c.swsp */ in host_signal_write()
49 case 0xe002: /* c.sdsp (rv64) / c.fswsp (rv32) */ in host_signal_write()
54 switch (insn & 0x7f) { in host_signal_write()
55 case 0x23: /* store */ in host_signal_write()
[all …]
/openbmc/qemu/hw/m68k/
H A Dnext-kbd.c41 #define CSR_INT 0x00800000
42 #define CSR_DATA 0x00400000
44 #define KD_KEYMASK 0x007f
45 #define KD_DIRECTION 0x0080 /* pressed or released */
46 #define KD_CNTL 0x0100
47 #define KD_LSHIFT 0x0200
48 #define KD_RSHIFT 0x0400
49 #define KD_LCOMM 0x0800
50 #define KD_RCOMM 0x1000
51 #define KD_LALT 0x2000
[all …]

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