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/openbmc/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-sun20i-d1.c18 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
19 SUNXI_FUNCTION(0x0, "gpio_in"),
20 SUNXI_FUNCTION(0x1, "gpio_out"),
21 SUNXI_FUNCTION(0x2, "pwm3"),
22 SUNXI_FUNCTION(0x3, "ir"), /* TX */
23 SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
24 SUNXI_FUNCTION(0x5, "spi1"), /* WP */
25 SUNXI_FUNCTION(0x6, "uart0"), /* TX */
26 SUNXI_FUNCTION(0x7, "uart2"), /* TX */
27 SUNXI_FUNCTION(0x8, "spdif"), /* OUT */
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/umc/
H A Dumc_6_7_0_sh_mask.h29 …C_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT 0x0
30 …_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT 0x10
31 …_UMC0_MCUMC_STATUST0__RESERV22__SHIFT 0x16
32 …_UMC0_MCUMC_STATUST0__AddrLsb__SHIFT 0x18
33 …_UMC0_MCUMC_STATUST0__RESERV30__SHIFT 0x1e
34 …_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT 0x20
35 …_UMC0_MCUMC_STATUST0__RESERV38__SHIFT 0x26
36 …_UMC0_MCUMC_STATUST0__Scrub__SHIFT 0x28
37 …_UMC0_MCUMC_STATUST0__RESERV41__SHIFT 0x29
38 …_UMC0_MCUMC_STATUST0__Poison__SHIFT 0x2b
[all …]
/openbmc/linux/arch/mips/math-emu/
H A Dieee754sp.c65 xm += 0x3 + ((xm >> 3) & 1); in ieee754sp_get_rounding()
66 /* xm += (xm&0x8)?0x4:0x3 */ in ieee754sp_get_rounding()
70 xm += 0x8; in ieee754sp_get_rounding()
74 xm += 0x8; in ieee754sp_get_rounding()
84 * xe is an unbiased exponent
87 union ieee754sp ieee754sp_format(int sn, int xe, unsigned int xm) in ieee754sp_format() argument
91 assert((xm >> (SP_FBITS + 1 + 3)) == 0); /* no excess */ in ieee754sp_format()
94 if (xe < SP_EMIN) { in ieee754sp_format()
96 int es = SP_EMIN - xe; in ieee754sp_format()
107 if (sn == 0) in ieee754sp_format()
[all …]
H A Dieee754dp.c65 xm += 0x3 + ((xm >> 3) & 1); in ieee754dp_get_rounding()
66 /* xm += (xm&0x8)?0x4:0x3 */ in ieee754dp_get_rounding()
70 xm += 0x8; in ieee754dp_get_rounding()
74 xm += 0x8; in ieee754dp_get_rounding()
84 * xe is an unbiased exponent
87 union ieee754dp ieee754dp_format(int sn, int xe, u64 xm) in ieee754dp_format() argument
91 assert((xm >> (DP_FBITS + 1 + 3)) == 0); /* no excess */ in ieee754dp_format()
94 if (xe < DP_EMIN) { in ieee754dp_format()
96 int es = DP_EMIN - xe; in ieee754dp_format()
107 if (sn == 0) in ieee754dp_format()
[all …]
H A Ddp_tlong.c37 return 0; in ieee754dp_tlong()
43 if (xe >= 63) { in ieee754dp_tlong()
45 if (xe == 63 && xs && xm == DP_HIDDEN_BIT) in ieee754dp_tlong()
46 return -0x8000000000000000LL; in ieee754dp_tlong()
53 if (xe > DP_FBITS) { in ieee754dp_tlong()
54 xm <<= xe - DP_FBITS; in ieee754dp_tlong()
55 } else if (xe < DP_FBITS) { in ieee754dp_tlong()
56 if (xe < -1) { in ieee754dp_tlong()
58 round = 0; in ieee754dp_tlong()
59 sticky = residue != 0; in ieee754dp_tlong()
[all …]
H A Dsp_tlong.c37 return 0; in ieee754sp_tlong()
43 if (xe >= 63) { in ieee754sp_tlong()
45 if (xe == 63 && xs && xm == SP_HIDDEN_BIT) in ieee754sp_tlong()
46 return -0x8000000000000000LL; in ieee754sp_tlong()
53 if (xe > SP_FBITS) { in ieee754sp_tlong()
54 xm <<= xe - SP_FBITS; in ieee754sp_tlong()
55 } else if (xe < SP_FBITS) { in ieee754sp_tlong()
56 if (xe < -1) { in ieee754sp_tlong()
58 round = 0; in ieee754sp_tlong()
59 sticky = residue != 0; in ieee754sp_tlong()
[all …]
H A Dsp_tint.c37 return 0; in ieee754sp_tint()
43 if (xe >= 31) { in ieee754sp_tint()
45 if (xe == 31 && xs && xm == SP_HIDDEN_BIT) in ieee754sp_tint()
46 return -0x80000000; in ieee754sp_tint()
53 if (xe > SP_FBITS) { in ieee754sp_tint()
54 xm <<= xe - SP_FBITS; in ieee754sp_tint()
56 if (xe < -1) { in ieee754sp_tint()
58 round = 0; in ieee754sp_tint()
59 sticky = residue != 0; in ieee754sp_tint()
60 xm = 0; in ieee754sp_tint()
[all …]
H A Ddp_tint.c37 return 0; in ieee754dp_tint()
43 if (xe > 31) { in ieee754dp_tint()
50 if (xe > DP_FBITS) { in ieee754dp_tint()
51 xm <<= xe - DP_FBITS; in ieee754dp_tint()
52 } else if (xe < DP_FBITS) { in ieee754dp_tint()
53 if (xe < -1) { in ieee754dp_tint()
55 round = 0; in ieee754dp_tint()
56 sticky = residue != 0; in ieee754dp_tint()
57 xm = 0; in ieee754dp_tint()
59 residue = xm << (64 - DP_FBITS + xe); in ieee754dp_tint()
[all …]
H A Ddp_sub.c104 /* normalize xm,xe */ in ieee754dp_sub()
122 if (xe > ye) { in ieee754dp_sub()
126 s = xe - ye; in ieee754dp_sub()
129 } else if (ye > xe) { in ieee754dp_sub()
133 s = ye - xe; in ieee754dp_sub()
135 xe += s; in ieee754dp_sub()
137 assert(xe == ye); in ieee754dp_sub()
138 assert(xe <= DP_EMAX); in ieee754dp_sub()
147 xe++; in ieee754dp_sub()
156 if (xm == 0) { in ieee754dp_sub()
[all …]
H A Ddp_add.c116 if (xe > ye) { in ieee754dp_add()
120 s = xe - ye; in ieee754dp_add()
123 } else if (ye > xe) { in ieee754dp_add()
127 s = ye - xe; in ieee754dp_add()
129 xe += s; in ieee754dp_add()
131 assert(xe == ye); in ieee754dp_add()
132 assert(xe <= DP_EMAX); in ieee754dp_add()
137 * leaving result in xm, xs and xe. in ieee754dp_add()
143 xe++; in ieee754dp_add()
152 if (xm == 0) in ieee754dp_add()
[all …]
H A Dsp_add.c116 if (xe > ye) { in ieee754sp_add()
120 s = xe - ye; in ieee754sp_add()
123 } else if (ye > xe) { in ieee754sp_add()
127 s = ye - xe; in ieee754sp_add()
129 xe += s; in ieee754sp_add()
131 assert(xe == ye); in ieee754sp_add()
132 assert(xe <= SP_EMAX); in ieee754sp_add()
137 * leaving result in xm, xs and xe. in ieee754sp_add()
151 if (xm == 0) in ieee754sp_add()
157 while ((xm >> (SP_FBITS + 3)) == 0) { in ieee754sp_add()
[all …]
H A Dsp_sub.c120 if (xe > ye) { in ieee754sp_sub()
124 s = xe - ye; in ieee754sp_sub()
127 } else if (ye > xe) { in ieee754sp_sub()
131 s = ye - xe; in ieee754sp_sub()
133 xe += s; in ieee754sp_sub()
135 assert(xe == ye); in ieee754sp_sub()
136 assert(xe <= SP_EMAX); in ieee754sp_sub()
153 if (xm == 0) { in ieee754sp_sub()
157 return ieee754sp_zero(0); /* other round modes => sign = 1 */ in ieee754sp_sub()
161 while ((xm >> (SP_FBITS + 3)) == 0) { in ieee754sp_sub()
[all …]
H A Ddp_fint.c15 int xe; in ieee754dp_fint() local
20 if (x == 0) in ieee754dp_fint()
21 return ieee754dp_zero(0); in ieee754dp_fint()
23 return ieee754dp_one(x < 0); in ieee754dp_fint()
25 return ieee754dp_ten(x < 0); in ieee754dp_fint()
27 xs = (x < 0); in ieee754dp_fint()
38 xe = DP_FBITS; in ieee754dp_fint()
39 while ((xm >> DP_FBITS) == 0) { in ieee754dp_fint()
41 xe--; in ieee754dp_fint()
43 return builddp(xs, xe + DP_EBIAS, xm & ~DP_HIDDEN_BIT); in ieee754dp_fint()
H A Dieee754int.h18 MADDF_NEGATE_PRODUCT = 1 << 0,
24 ieee754_csr.cx = 0; in ieee754_clearcx()
46 unsigned int xm; int xe; int xs __maybe_unused; int xc
60 if (vm == 0) \
78 #define EXPLODEXSP EXPLODESP(x, xc, xs, xe, xm)
84 u64 xm; int xe; int xs __maybe_unused; int xc
98 if (vm == 0) \
116 #define EXPLODEXDP EXPLODEDP(x, xc, xs, xe, xm)
126 vm = 0; \
137 vm = 0; \
[all …]
/openbmc/u-boot/include/configs/
H A Dhsdk.h15 #define ARC_PERIPHERAL_BASE 0xF0000000
16 #define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000)
17 #define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000)
24 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
29 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
33 #define CONFIG_SYS_LOAD_ADDR 0x82000000
57 "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \
61 "; fi\0" \
62 "core_dccm_0=0x10\0" \
63 "core_dccm_1=0x6\0" \
[all …]
/openbmc/linux/Documentation/gpu/rfc/
H A Dxe.rst2 Xe – Merge Acceptance Plan
4 Xe is a new driver for Intel GPUs that supports both integrated and
5 discrete platforms starting with Tiger Lake (first Intel Xe Architecture).
7 This document aims to establish a merge plan for the Xe, by writing down clear
10 Xe – Overview
12 The main motivation of Xe is to have a fresh base to work from that is
38 https://gitlab.freedesktop.org/drm/xe/kernel (branch drm-xe-next)
40 Xe – Platforms
42 Currently, Xe is already functional and has experimental support for multiple
47 During a transition period, platforms will be supported by both Xe and i915.
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_sh_mask.h26 …C_TAG_CNT__DED_COUNT__SHIFT 0x0
27 …C_TAG_CNT__SEC_COUNT__SHIFT 0x2
28 …T__DED_COUNT_MASK 0x00000003L
29 …T__SEC_COUNT_MASK 0x0000000CL
31 …C_ROQ_CNT__DED_COUNT_ME1__SHIFT 0x0
32 …C_ROQ_CNT__SEC_COUNT_ME1__SHIFT 0x2
33 …C_ROQ_CNT__DED_COUNT_ME2__SHIFT 0x4
34 …C_ROQ_CNT__SEC_COUNT_ME2__SHIFT 0x6
35 …T__DED_COUNT_ME1_MASK 0x00000003L
36 …T__SEC_COUNT_ME1_MASK 0x0000000CL
[all …]
/openbmc/qemu/tests/tcg/i386/
H A Dtest-i386-f2xm1.c14 { 0x4.1481697ac693aa6p-4L, 0x3.17ec9f8454896518p-4L, 0x3.17ec9f845489651cp-4L },
15 { -0xd.84a873b14b9c0e2p-4L, -0x7.1788c46ac260d948p-4L, -0x7.1788c46ac260d94p-4L },
16 { 0xa.a3dc18b1eff7e8ap-188L, 0x7.6009241b9e21523p-188L, 0x7.6009241b9e215238p-188L },
17 { -0xe.846aeb6f58174d5p-92L, -0xa.1006405817acc33p-92L, -0xa.1006405817acc32p-92L },
18 { 0x5.4459f2ac77bb0978p-4L, 0x4.19d3ce7fd5b90ac8p-4L, 0x4.19d3ce7fd5b90adp-4L },
19 { -0xb.79bece734a62216p-4L, -0x6.4489a7fc150c0fp-4L, -0x6.4489a7fc150c0ef8p-4L },
20 { 0xa.ab48f9ef732f5c4p-4L, 0x9.66acd7d4b7cf015p-4L, 0x9.66acd7d4b7cf016p-4L },
21 { -0xb.8204e63359a46e6p-4L, -0x6.48060f0a504e3488p-4L, -0x6.48060f0a504e348p-4L },
22 { 0xd.c732865701ae935p-4L, 0xd.103bc1a15cd9f71p-4L, 0xd.103bc1a15cd9f72p-4L },
23 { -0x1.6296e8ff499827a2p-4L, -0xe.e8dc973f0bce9d1p-8L, -0xe.e8dc973f0bce9dp-8L },
[all …]
/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Dmarvell,mvebu-pinctrl.txt21 When the function value for a specific pin equal 0xFF,
36 reg = <0x6F4000 0x10>;
40 * SPI0 [0-3]
44 /* 0 1 2 3 4 5 6 7 8 9 */
45 pin-func = < 3 3 3 3 3 3 0 0 0 0
46 0 3 0 0 0 0 0 0 0 3>;
58 reg = <0x440000 0x20>;
60 max-func = <0xf>;
62 * [0-31] = 0xff: Keep default CP0_shared_pins:
71 * [40-41] SATA[0/1]_PRESENT_ACTIVEn
[all …]
/openbmc/linux/drivers/ata/pata_parport/
H A Daten.c20 #define j44(a,b) ((((a>>4)&0x0f)|(b&0xf0))^0x88)
23 * cont = 0 - access the IDE register file
26 static int cont_map[2] = { 0x08, 0x20 };
30 int r = regr + cont_map[cont] + 0x80; in aten_write_regr()
32 w0(r); w2(0xe); w2(6); w0(val); w2(7); w2(6); w2(0xc); in aten_write_regr()
39 r = regr + cont_map[cont] + 0x40; in aten_read_regr()
43 case 0: in aten_read_regr()
44 w0(r); w2(0xe); w2(6); in aten_read_regr()
45 w2(7); w2(6); w2(0); in aten_read_regr()
46 a = r1(); w0(0x10); b = r1(); w2(0xc); in aten_read_regr()
[all …]
/openbmc/qemu/scripts/
H A Dxen-detect.c13 xd = xendevicemodel_open(0, 0); in main()
14 xendevicemodel_pin_memory_cacheattr(xd, 0, 0, 0, 0); in main()
16 xfmem = xenforeignmemory_open(0, 0); in main()
17 xenforeignmemory_map_resource(xfmem, 0, 0, 0, 0, 0, NULL, 0, 0); in main()
19 return 0; in main()
29 xfmem = xenforeignmemory_open(0, 0); in main()
30 xenforeignmemory_map2(xfmem, 0, 0, 0, 0, 0, 0, 0); in main()
31 xentoolcore_restrict_all(0); in main()
33 return 0; in main()
43 xd = xendevicemodel_open(0, 0); in main()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/athub/
H A Dathub_3_0_0_sh_mask.h29 …R_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
30 …RTR0__BASE_ADDR_MASK 0x7FFFFFFFL
32 …R_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
33 …RTR1__BASE_ADDR_MASK 0x7FFFFFFFL
35 …R_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
36 …RTR2__BASE_ADDR_MASK 0x7FFFFFFFL
38 …R_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
39 …RTR3__BASE_ADDR_MASK 0x7FFFFFFFL
41 …R_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
42 …RTR4__BASE_ADDR_MASK 0x7FFFFFFFL
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-7040-db-nand.dts45 * Boot device: NAND, 0xE (SW3)
67 reg = <0x0 0x0 0x0 0x80000000>;
73 * SDIO [0-5]
76 /* 0 1 2 3 4 5 6 7 8 9 */
77 pin-func = < 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0
78 0x0 0x3 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x3 >;
92 pinctrl-0 = <&cpm_i2c0_pins>;
99 * AUDIO [0-5]
115 /* 0 1 2 3 4 5 6 7 8 9 */
116 pin-func = < 0x2 0x2 0x2 0x2 0x2 0x2 0x3 0x3 0x3 0x3
[all …]
H A Darmada-7040-db.dts45 * Boot device: SPI NOR, 0x32 (SW3)
66 reg = <0x0 0x0 0x0 0x80000000>;
72 * SDIO [0-5]
75 /* 0 1 2 3 4 5 6 7 8 9 */
76 pin-func = < 1 1 1 1 1 1 0 0 0 0
77 0 3 0 0 0 0 0 0 0 3 >;
91 pinctrl-0 = <&cpm_i2c0_pins>;
98 * TDM [0-11]
108 /* 0 1 2 3 4 5 6 7 8 9 */
110 4 4 0 3 3 3 3 0 0 0
[all …]
/openbmc/linux/drivers/iio/dac/
H A Dad7293.c27 #define AD7293_REG_NO_OP (AD7293_R1B | AD7293_PAGE(0x0) | 0x0)
28 #define AD7293_REG_PAGE_SELECT (AD7293_R1B | AD7293_PAGE(0x0) | 0x1)
29 #define AD7293_REG_CONV_CMD (AD7293_R2B | AD7293_PAGE(0x0) | 0x2)
30 #define AD7293_REG_RESULT (AD7293_R1B | AD7293_PAGE(0x0) | 0x3)
31 #define AD7293_REG_DAC_EN (AD7293_R1B | AD7293_PAGE(0x0) | 0x4)
32 #define AD7293_REG_DEVICE_ID (AD7293_R2B | AD7293_PAGE(0x0) | 0xC)
33 #define AD7293_REG_SOFT_RESET (AD7293_R2B | AD7293_PAGE(0x0) | 0xF)
35 /* AD7293 Register Map Page 0x0 */
36 #define AD7293_REG_VIN0 (AD7293_R2B | AD7293_PAGE(0x0) | 0x10)
37 #define AD7293_REG_VIN1 (AD7293_R2B | AD7293_PAGE(0x0) | 0x11)
[all …]

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