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/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dddrphy_train.c16 int i = 0; in ddr_cfg_phy()
17 int j = 0; in ddr_cfg_phy()
22 for (i = 0; i < num; i++) { in ddr_cfg_phy()
30 for (i = 0; i < dram_timing->fsp_msg_num; i++) { in ddr_cfg_phy()
36 dwc_ddrphy_apb_wr(0xd0000, 0x0); in ddr_cfg_phy()
42 for (j = 0; j < num; j++) { in ddr_cfg_phy()
57 dwc_ddrphy_apb_wr(0xd0000, 0x1); in ddr_cfg_phy()
58 dwc_ddrphy_apb_wr(0xd0099, 0x9); in ddr_cfg_phy()
59 dwc_ddrphy_apb_wr(0xd0099, 0x1); in ddr_cfg_phy()
60 dwc_ddrphy_apb_wr(0xd0099, 0x0); in ddr_cfg_phy()
[all …]
H A Dhelper.c22 #define IMEM_OFFSET_ADDR 0x00050000
23 #define DMEM_OFFSET_ADDR 0x00054000
24 #define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
30 u32 error = 0; in ddr_load_train_firmware()
32 unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0; in ddr_load_train_firmware()
38 for (i = 0x0; i < IMEM_LEN; ) { in ddr_load_train_firmware()
40 writew(tmp32 & 0x0000ffff, pr_to32); in ddr_load_train_firmware()
42 writew((tmp32 >> 16) & 0x0000ffff, pr_to32); in ddr_load_train_firmware()
50 for (i = 0x0; i < DMEM_LEN; ) { in ddr_load_train_firmware()
52 writew(tmp32 & 0x0000ffff, pr_to32); in ddr_load_train_firmware()
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/cfg/
H A Dsc.c19 #define IWL_SC_NVM_VERSION 0x0a1d
22 #define IWL_SC_DCCM_OFFSET 0x800000 /* LMAC1 */
23 #define IWL_SC_DCCM_LEN 0x10000 /* LMAC1 */
24 #define IWL_SC_DCCM2_OFFSET 0x880000
25 #define IWL_SC_DCCM2_LEN 0x8000
26 #define IWL_SC_SMEM_OFFSET 0x400000
27 #define IWL_SC_SMEM_LEN 0xD0000
79 .mac_addr_from_csr = 0x30, \
85 .min_umac_error_event_table = 0xD0000, \
86 .d3_debug_data_base_addr = 0x401000, \
[all …]
H A Dbz.c19 #define IWL_BZ_NVM_VERSION 0x0a1d
22 #define IWL_BZ_DCCM_OFFSET 0x800000 /* LMAC1 */
23 #define IWL_BZ_DCCM_LEN 0x10000 /* LMAC1 */
24 #define IWL_BZ_DCCM2_OFFSET 0x880000
25 #define IWL_BZ_DCCM2_LEN 0x8000
26 #define IWL_BZ_SMEM_OFFSET 0x400000
27 #define IWL_BZ_SMEM_LEN 0xD0000
82 .mac_addr_from_csr = 0x30, \
88 .min_umac_error_event_table = 0xD0000, \
89 .d3_debug_data_base_addr = 0x401000, \
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-t5325.dts23 reg = <0x00000000 0x20000000>;
33 pinctrl-0 = <&pmx_i2s &pmx_sysrst>;
76 flash@0 {
81 reg = <0>;
82 mode = <0>;
84 partition@0 {
85 reg = <0x0 0x80000>;
90 reg = <0x80000 0x40000>;
95 reg = <0xc0000 0x10000>;
100 reg = <0xd0000 0x10000>;
[all …]
/openbmc/linux/drivers/staging/media/atomisp/pci/
H A Dstr2mem_defs.h19 #define _STR2MEM_CRUN_BIT 0x100000
20 #define _STR2MEM_CMD_BITS 0x0F0000
21 #define _STR2MEM_COUNT_BITS 0x00FFFF
23 #define _STR2MEM_BLOCKS_CMD 0xA0000
24 #define _STR2MEM_PACKETS_CMD 0xB0000
25 #define _STR2MEM_BYTES_CMD 0xC0000
26 #define _STR2MEM_BYTES_FROM_PACKET_CMD 0xD0000
28 #define _STR2MEM_SOFT_RESET_REG_ID 0
/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing.c15 { DDRC_DBG1(0), 0x00000001 },
16 { DDRC_PWRCTL(0), 0x00000001 },
17 { DDRC_MSTR(0), 0xa3080020 },
18 { DDRC_MSTR2(0), 0x00000000 },
19 { DDRC_RFSHTMG(0), 0x006100E0 },
20 { DDRC_INIT0(0), 0xC003061B },
21 { DDRC_INIT1(0), 0x009D0000 },
22 { DDRC_INIT3(0), 0x00D4002D },
24 { DDRC_INIT4(0), 0x00330008 },
26 { DDRC_INIT4(0), 0x00310008 },
[all …]
H A Dlpddr4_timing_b0.c16 { DDRC_DBG1(0), 0x00000001 },
18 { DDRC_PWRCTL(0), 0x00000001 },
19 { DDRC_MSTR(0), 0xa3080020 },
20 { DDRC_MSTR2(0), 0x00000000 },
21 { DDRC_RFSHTMG(0), 0x006100E0 },
22 { DDRC_INIT0(0), 0xC003061B },
23 { DDRC_INIT1(0), 0x009D0000 },
24 { DDRC_INIT3(0), 0x00D4002D },
26 { DDRC_INIT4(0), 0x00330008 },
28 { DDRC_INIT4(0), 0x00310008 },
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm53340-ubnt-unifi-switch8.dts22 memory@0 {
24 reg = <0x00000000 0x08000000>,
25 <0x68000000 0x08000000>;
35 bspi-sel = <0>;
37 flash: flash@0 {
39 reg = <0>;
46 partition@0 {
48 reg = <0x0 0xc0000>;
53 reg = <0xc0000 0x10000>;
58 reg = <0xd0000 0x10000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/dove/
H A Dpmu.txt24 - #power-domain-cells: must be 0.
35 reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
43 #power-domain-cells = <0>;
44 marvell,pmu_pwr_mask = <0x00000008>;
45 marvell,pmu_iso_mask = <0x00000001>;
50 #power-domain-cells = <0>;
51 marvell,pmu_pwr_mask = <0x00000004>;
52 marvell,pmu_iso_mask = <0x00000002>;
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx8qxp-lpcg.h11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
[all …]
/openbmc/u-boot/include/configs/
H A Dds414.h28 #define CONFIG_SYS_I2C_SLAVE 0x0
34 #define CONFIG_ENV_OFFSET 0x7E0000 /* RedBoot config partition in DTS */
72 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
73 * 0x4000.4030 bin_hdr start address
74 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
75 * 0x4007.fffc BootROM stack top
77 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
83 #define CONFIG_SPL_TEXT_BASE 0x40004030
84 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
86 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
[all …]
/openbmc/qemu/include/hw/pci-host/
H A Dpam.h35 * 0xa0000 - 0xbffff compatible SMRAM
37 * 0xc0000 - 0xc3fff Expansion area memory segments
38 * 0xc4000 - 0xc7fff
39 * 0xc8000 - 0xcbfff
40 * 0xcc000 - 0xcffff
41 * 0xd0000 - 0xd3fff
42 * 0xd4000 - 0xd7fff
43 * 0xd8000 - 0xdbfff
44 * 0xdc000 - 0xdffff
45 * 0xe0000 - 0xe3fff Extended System BIOS Area Memory Segments
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7-mba7.dtsi25 gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>;
35 button-0 {
201 pinctrl-0 = <&pinctrl_ecspi1>;
202 cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>,
209 pinctrl-0 = <&pinctrl_ecspi2>;
215 pinctrl-0 = <&pinctrl_enet1>;
226 #size-cells = <0>;
228 ethphy1_0: ethernet-phy@0 {
230 reg = <0>;
245 uboot@0 {
[all …]
/openbmc/linux/Documentation/sound/cards/
H A Dmultisound.sh77 # 0x250, 0x260 or 0x270. This port can be disabled to have the card
96 # to obtain one with the command `pnpdump 1 0x203' -- this may vary
107 # io base 0x210, irq 5 and mem 0xd8000, and also sets the Kurzweil
108 # synth to 0x330 and irq 9 (may need editing for your system):
110 # (READPORT 0x0203)
115 # (CONFIGURE BVJ0440/-1 (LD 0
116 # (INT 0 (IRQ 5 (MODE +E))) (IO 0 (BASE 0x0210)) (MEM 0 (BASE 0x0d8000))
121 # (IO 0 (BASE 0x0330)) (INT 0 (IRQ 9 (MODE +E)))
140 # If you specify cfg=0x250 for the snd-msnd-pinnacle module, it
143 # on the card to 0x250, 0x260 or 0x270).
[all …]
/openbmc/linux/arch/arm/mach-dove/
H A Ddove.h14 * e0000000 @runtime 128M PCIe-0 Memory space
18 * f2000000 fee00000 1M PCIe-0 I/O space
22 #define DOVE_CESA_PHYS_BASE 0xc8000000
23 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
26 #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
29 #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
32 #define DOVE_BOOTROM_PHYS_BASE 0xf8000000
35 #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
36 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
39 #define DOVE_SB_REGS_PHYS_BASE 0xf1000000
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/include/mach/
H A Dsoc.h13 #define SOC_MV78230_ID 0x7823
14 #define SOC_MV78260_ID 0x7826
15 #define SOC_MV78460_ID 0x7846
16 #define SOC_88F6720_ID 0x6720
17 #define SOC_88F6810_ID 0x6810
18 #define SOC_88F6820_ID 0x6820
19 #define SOC_88F6828_ID 0x6828
20 #define SOC_98DX3236_ID 0xf410
21 #define SOC_98DX3336_ID 0xf400
22 #define SOC_98DX4251_ID 0xfc00
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dmarvell,nand-controller.yaml66 minimum: 0
71 - minimum: 0
156 reg = <0xd0000 0x54>;
158 #size-cells = <0>;
160 clocks = <&coredivclk 0>;
162 nand@0 {
163 reg = <0>;
165 nand-rb = <0>;
177 partition@0 {
179 reg = <0x00000000 0x40000000>;
[all …]
/openbmc/linux/Documentation/networking/
H A Dgeneric-hdlc.rst140 insmod n2 hw=0x300,10,0xD0000,01
148 insmod c101 hw=9,0xdc000
/openbmc/u-boot/arch/x86/include/asm/arch-quark/acpi/
H A Dsouthcluster.asl11 Name(_ADR, 0)
12 Name(_BBN, 0)
18 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
20 /* IO Region 0 */
22 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
25 IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
29 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
31 /* VGA memory (0xa0000-0xbffff) */
34 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
35 0x00020000, , , ASEG)
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D07325 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
56 $QEMU_IO -c "write -P 0xa5 0 $size" "$TEST_IMG.base" | _filter_qemu_io
61 $QEMU_IO -c "write -P 0x11 0 0x10000" "$TEST_IMG" | _filter_qemu_io
62 $QEMU_IO -c "write -P 0x11 0x10000 0x10000" "$TEST_IMG.base" | _filter_qemu_io
64 $QEMU_IO -c "read -P 0x11 0 0x20000" "$TEST_IMG" | _filter_qemu_io
69 $QEMU_IO -c "write -P 0x22 0x20000 0x10000" "$TEST_IMG" | _filter_qemu_io
70 $QEMU_IO -c "write -c -P 0x22 0x30000 0x10000" "$TEST_IMG" | _filter_qemu_io
72 $QEMU_IO -c "read -P 0x22 0x20000 0x20000" "$TEST_IMG" | _filter_qemu_io
77 $QEMU_IO -c "write -P 0x33 0x40000 0x20000" "$TEST_IMG" | _filter_qemu_io
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A Dmx3x.h36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_mixer.h18 #define SUN8I_MIXER_GLOBAL_CTL 0x0
19 #define SUN8I_MIXER_GLOBAL_STATUS 0x4
20 #define SUN8I_MIXER_GLOBAL_DBUFF 0x8
21 #define SUN8I_MIXER_GLOBAL_SIZE 0xc
23 #define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0)
25 #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
27 #define DE2_MIXER_UNIT_SIZE 0x6000
28 #define DE3_MIXER_UNIT_SIZE 0x3000
30 #define DE2_BLD_BASE 0x1000
31 #define DE2_CH_BASE 0x2000
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-baytrail/acpi/
H A Dsouthcluster.asl14 Name(_ADR, 0)
15 Name(_BBN, 0)
21 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
23 /* IO Region 0 */
25 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
28 IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
32 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
34 /* VGA memory (0xa0000-0xbffff) */
37 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
38 0x00020000, , , ASEG)
[all …]
/openbmc/linux/arch/mips/include/asm/sn/sn0/
H A Daddrs.h57 #define NASID_BITMASK (0x1ffLL)
62 #define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
63 #define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
70 #define NASID_BITMASK (0xffLL)
76 #define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
77 #define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
90 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
106 #define BWIN_WIDGET_MASK 0x7
150 #define MISC_PROM_BASE PHYS_TO_K0(0x01300000)
151 #define MISC_PROM_SIZE 0x200000
[all …]

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