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/openbmc/qemu/tests/qtest/
H A Dam53c974-test.c21 qtest_outl(s, 0xcf8, 0x80001004); in test_cmdfifo_underflow_ok()
22 qtest_outw(s, 0xcfc, 0x01); in test_cmdfifo_underflow_ok()
23 qtest_outl(s, 0xcf8, 0x8000100e); in test_cmdfifo_underflow_ok()
24 qtest_outl(s, 0xcfc, 0x8a000000); in test_cmdfifo_underflow_ok()
25 qtest_outl(s, 0x8a09, 0x42000000); in test_cmdfifo_underflow_ok()
26 qtest_outl(s, 0x8a0d, 0x00); in test_cmdfifo_underflow_ok()
27 qtest_outl(s, 0x8a0b, 0x1000); in test_cmdfifo_underflow_ok()
37 qtest_outl(s, 0xcf8, 0x80001010); in test_cmdfifo_underflow2_ok()
38 qtest_outl(s, 0xcfc, 0xc000); in test_cmdfifo_underflow2_ok()
39 qtest_outl(s, 0xcf8, 0x80001004); in test_cmdfifo_underflow2_ok()
[all …]
H A Dfuzz-lsi53c895a-test.c25 qtest_outl(s, 0xcf8, 0x80000804); /* PCI Command Register */ in test_lsi_dma_reentrancy()
26 qtest_outw(s, 0xcfc, 0x7); /* Enables accesses */ in test_lsi_dma_reentrancy()
27 qtest_outl(s, 0xcf8, 0x80000814); /* Memory Bar 1 */ in test_lsi_dma_reentrancy()
28 qtest_outl(s, 0xcfc, 0xff100000); /* Set MMIO Address*/ in test_lsi_dma_reentrancy()
29 qtest_outl(s, 0xcf8, 0x80000818); /* Memory Bar 2 */ in test_lsi_dma_reentrancy()
30 qtest_outl(s, 0xcfc, 0xff000000); /* Set RAM Address*/ in test_lsi_dma_reentrancy()
31 qtest_writel(s, 0xff000000, 0xc0000024); in test_lsi_dma_reentrancy()
32 qtest_writel(s, 0xff000114, 0x00000080); in test_lsi_dma_reentrancy()
33 qtest_writel(s, 0xff00012c, 0xff000000); in test_lsi_dma_reentrancy()
34 qtest_writel(s, 0xff000004, 0xff000114); in test_lsi_dma_reentrancy()
[all …]
H A Dfuzz-megasas-test.c25 qtest_outl(s, 0xcf8, 0x80001818); in test_lp1878263_megasas_zero_iov_cnt()
26 qtest_outl(s, 0xcfc, 0xc101); in test_lp1878263_megasas_zero_iov_cnt()
27 qtest_outl(s, 0xcf8, 0x8000181c); in test_lp1878263_megasas_zero_iov_cnt()
28 qtest_outl(s, 0xcf8, 0x80001804); in test_lp1878263_megasas_zero_iov_cnt()
29 qtest_outw(s, 0xcfc, 0x7); in test_lp1878263_megasas_zero_iov_cnt()
30 qtest_outl(s, 0xcf8, 0x8000186a); in test_lp1878263_megasas_zero_iov_cnt()
31 qtest_writeb(s, 0x14, 0xfe); in test_lp1878263_megasas_zero_iov_cnt()
32 qtest_writeb(s, 0x0, 0x02); in test_lp1878263_megasas_zero_iov_cnt()
33 qtest_outb(s, 0xc1c0, 0x17); in test_lp1878263_megasas_zero_iov_cnt()
48 qtest_outl(s, 0xcf8, 0x80000818); in test_gitlab_issue521_megasas_sgl_ovf()
[all …]
H A Dfuzz-sdcard-test.c24 " -drive if=none,index=0,file=null-co://,format=raw,id=d0"); in oss_fuzz_29225()
26 qtest_outl(s, 0xcf8, 0x80001010); in oss_fuzz_29225()
27 qtest_outl(s, 0xcfc, 0xd0690); in oss_fuzz_29225()
28 qtest_outl(s, 0xcf8, 0x80001003); in oss_fuzz_29225()
29 qtest_outl(s, 0xcf8, 0x80001013); in oss_fuzz_29225()
30 qtest_outl(s, 0xcfc, 0xffffffff); in oss_fuzz_29225()
31 qtest_outl(s, 0xcf8, 0x80001003); in oss_fuzz_29225()
32 qtest_outl(s, 0xcfc, 0x3effe00); in oss_fuzz_29225()
34 qtest_bufwrite(s, 0xff0d062c, "\xff", 0x1); in oss_fuzz_29225()
35 qtest_bufwrite(s, 0xff0d060f, "\xb7", 0x1); in oss_fuzz_29225()
[all …]
H A Dfuzz-virtio-scsi-test.c25 qtest_outl(s, 0xcf8, 0x80001811); in test_mmio_oob_from_memory_region_cache()
26 qtest_outb(s, 0xcfc, 0x6e); in test_mmio_oob_from_memory_region_cache()
27 qtest_outl(s, 0xcf8, 0x80001824); in test_mmio_oob_from_memory_region_cache()
28 qtest_outl(s, 0xcf8, 0x80001813); in test_mmio_oob_from_memory_region_cache()
29 qtest_outl(s, 0xcfc, 0xa080000); in test_mmio_oob_from_memory_region_cache()
30 qtest_outl(s, 0xcf8, 0x80001802); in test_mmio_oob_from_memory_region_cache()
31 qtest_outl(s, 0xcfc, 0x5a175a63); in test_mmio_oob_from_memory_region_cache()
32 qtest_outb(s, 0x6e08, 0x9e); in test_mmio_oob_from_memory_region_cache()
33 qtest_writeb(s, 0x9f003, 0xff); in test_mmio_oob_from_memory_region_cache()
34 qtest_writeb(s, 0x9f004, 0x01); in test_mmio_oob_from_memory_region_cache()
[all …]
H A Dlpc-ich9-test.c21 qtest_outl(s, 0xcf8, 0x8000f840); /* PMBASE */ in test_lp1878642_pci_bus_get_irq_level_assert()
22 qtest_outl(s, 0xcfc, 0x5d00); in test_lp1878642_pci_bus_get_irq_level_assert()
23 qtest_outl(s, 0xcf8, 0x8000f844); /* ACPI_CTRL */ in test_lp1878642_pci_bus_get_irq_level_assert()
24 qtest_outl(s, 0xcfc, 0xeb); in test_lp1878642_pci_bus_get_irq_level_assert()
25 qtest_outw(s, 0x5d02, 0x205d); in test_lp1878642_pci_bus_get_irq_level_assert()
35 if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { in main()
H A Dvirtio-balloon-test.c23 qtest_outl(s, 0xcf8, 0x80000890); in oss_fuzz_71649()
24 qtest_outl(s, 0xcfc, 0x2); in oss_fuzz_71649()
25 qtest_outl(s, 0xcf8, 0x80000891); in oss_fuzz_71649()
26 qtest_inl(s, 0xcfc); in oss_fuzz_71649()
H A Dfuzz-e1000e-test.c22 qtest_outl(s, 0xcf8, 0x80001010); in test_lp1879531_eth_get_rss_ex_dst_addr()
23 qtest_outl(s, 0xcfc, 0xe1020000); in test_lp1879531_eth_get_rss_ex_dst_addr()
24 qtest_outl(s, 0xcf8, 0x80001004); in test_lp1879531_eth_get_rss_ex_dst_addr()
25 qtest_outw(s, 0xcfc, 0x7); in test_lp1879531_eth_get_rss_ex_dst_addr()
26 qtest_writeb(s, 0x25, 0x86); in test_lp1879531_eth_get_rss_ex_dst_addr()
27 qtest_writeb(s, 0x26, 0xdd); in test_lp1879531_eth_get_rss_ex_dst_addr()
28 qtest_writeb(s, 0x4f, 0x2b); in test_lp1879531_eth_get_rss_ex_dst_addr()
30 qtest_writel(s, 0xe1020030, 0x190002e1); in test_lp1879531_eth_get_rss_ex_dst_addr()
31 qtest_writew(s, 0xe102003a, 0x0807); in test_lp1879531_eth_get_rss_ex_dst_addr()
32 qtest_writel(s, 0xe1020048, 0x12077cdd); in test_lp1879531_eth_get_rss_ex_dst_addr()
[all …]
H A Dintel-hda-test.c16 #define CODEC_DEVICES " -device hda-output,bus=" HDA_ID ".0," AUDIODEV_REF \
17 " -device hda-micro,bus=" HDA_ID ".0," AUDIODEV_REF \
18 " -device hda-duplex,bus=" HDA_ID ".0," AUDIODEV_REF
31 "-device ich9-intel-hda,bus=pcie.0,addr=1b.0,id=" in ich9_test()
49 qtest_outl(s, 0xcf8, 0x80000804); in test_issue542_ich6()
50 qtest_outw(s, 0xcfc, 0x06); in test_issue542_ich6()
51 qtest_bufwrite(s, 0xff0d060f, "\x03", 1); in test_issue542_ich6()
52 qtest_bufwrite(s, 0x0, "\x12", 1); in test_issue542_ich6()
53 qtest_bufwrite(s, 0x2, "\x2a", 1); in test_issue542_ich6()
54 qtest_writeb(s, 0x0, 0x12); in test_issue542_ich6()
[all …]
/openbmc/linux/arch/x86/pci/
H A Ddirect.c18 (0x80000000 | ((reg & 0xF00) << 16) | (bus << 16) \
19 | (devfn << 8) | (reg & 0xFC))
33 outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); in pci_conf1_read()
37 *value = inb(0xCFC + (reg & 3)); in pci_conf1_read()
40 *value = inw(0xCFC + (reg & 2)); in pci_conf1_read()
43 *value = inl(0xCFC); in pci_conf1_read()
49 return 0; in pci_conf1_read()
62 outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); in pci_conf1_write()
66 outb((u8)value, 0xCFC + (reg & 3)); in pci_conf1_write()
69 outw((u16)value, 0xCFC + (reg & 2)); in pci_conf1_write()
[all …]
H A Dearly.c14 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config()
15 v = inl(0xcfc); in read_pci_config()
22 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config_byte()
23 v = inb(0xcfc + (offset&3)); in read_pci_config_byte()
30 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config_16()
31 v = inw(0xcfc + (offset&2)); in read_pci_config_16()
38 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in write_pci_config()
39 outl(val, 0xcfc); in write_pci_config()
44 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in write_pci_config_byte()
45 outb(val, 0xcfc + (offset&3)); in write_pci_config_byte()
[all …]
H A Dacpi.c32 return 0; in set_use_crs()
38 return 0; in set_nouse_crs()
45 return 0; in set_ignore_seg()
53 return 0; in set_no_e820()
202 if (year >= 0 && year < 2008 && iomem_resource.end <= 0xffffffff) in pci_acpi_crs_quirks()
304 "usb4-host-interface", 0); in pcie_has_usb4_host_interface()
319 case 0x8a1d: in pcie_has_usb4_host_interface()
320 case 0x8a1f: in pcie_has_usb4_host_interface()
321 case 0x8a21: in pcie_has_usb4_host_interface()
322 case 0x8a23: in pcie_has_usb4_host_interface()
[all …]
/openbmc/qemu/tests/qtest/libqos/
H A Dpci-pc.c21 #define ACPI_PCIHP_ADDR 0xae00
22 #define PCI_EJ_BASE 0x0008
62 qtest_outl(bus->qts, addr, val & 0xffffffff); in qpci_pc_pio_writeq()
79 qtest_outl(bus->qts, 0xcf8, (1U << 31) | (devfn << 8) | offset); in qpci_pc_config_readb()
80 return qtest_inb(bus->qts, 0xcfc); in qpci_pc_config_readb()
85 qtest_outl(bus->qts, 0xcf8, (1U << 31) | (devfn << 8) | offset); in qpci_pc_config_readw()
86 return qtest_inw(bus->qts, 0xcfc); in qpci_pc_config_readw()
91 qtest_outl(bus->qts, 0xcf8, (1U << 31) | (devfn << 8) | offset); in qpci_pc_config_readl()
92 return qtest_inl(bus->qts, 0xcfc); in qpci_pc_config_readl()
97 qtest_outl(bus->qts, 0xcf8, (1U << 31) | (devfn << 8) | offset); in qpci_pc_config_writeb()
[all …]
/openbmc/u-boot/board/google/common/
H A Dearly_init.S10 mov $0x1b, %ecx
12 and $0x100, %eax
16 mov $0x8000f8f0, %eax
17 mov $0xcf8, %dx
19 mov $0xfed1c001, %eax
20 mov $0xcfc, %dx
22 mov $0xfed1f410, %esp
24 and $0xfffffffb, %eax
/openbmc/u-boot/arch/x86/include/asm/
H A Dpci.h13 #define PCI_REG_ADDR 0xcf8
14 #define PCI_REG_DATA 0xcfc
16 #define PCI_CFG_EN 0x80000000
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dlantiq,xrx200-net.yaml14 pattern: "^ethernet@[0-9a-f]+$"
36 const: 0
52 #size-cells = <0>;
54 reg = <0xe10b308 0xcf8>;
/openbmc/qemu/hw/pci-host/
H A Di440fx.c63 #define I440FX_PAM 0x59
65 #define I440FX_SMRAM 0x72
73 #define I440FX_COREBOOT_RAM_SIZE 0x57
77 dev->config[I440FX_SMRAM] = 0x02; in i440fx_realize()
90 for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) { in i440fx_update_memory_mappings()
120 return 0; in i440fx_post_load()
146 val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole); in i440fx_pcihost_get_pci_hole_start()
160 val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1; in i440fx_pcihost_get_pci_hole_end()
181 value = range_is_empty(&w64) ? 0 : range_lob(&w64); in i440fx_pcihost_get_pci_hole64_start_value()
214 value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; in i440fx_pcihost_get_pci_hole64_end()
[all …]
/openbmc/linux/arch/ia64/pci/
H A Dpci.c51 u64 addr, data = 0; in raw_pci_read()
59 mode = 0; in raw_pci_read()
68 if (result != 0) in raw_pci_read()
72 return 0; in raw_pci_read()
86 mode = 0; in raw_pci_write()
94 if (result != 0) in raw_pci_write()
96 return 0; in raw_pci_write()
129 if (phys_base == 0) in new_space()
130 return 0; /* legacy I/O port space */ in new_space()
132 mmio_base = (u64) ioremap(phys_base, 0); in new_space()
[all …]
/openbmc/linux/arch/x86/kernel/
H A Dreboot_fixups_32.c20 /* writing 1 to the reset control register, 0x44 causes the in cs5530a_warm_reset()
22 pci_write_config_byte(dev, 0x44, 0x1); in cs5530a_warm_reset()
38 outl(0x80003840, 0xCF8); in rdc321x_reset()
40 i = inl(0xCFC); in rdc321x_reset()
42 i |= 0x1600; in rdc321x_reset()
43 outl(i, 0xCFC); in rdc321x_reset()
44 outb(1, 0x92); in rdc321x_reset()
51 for (i = 0; i < 10; i++) { in ce4100_reset()
52 outb(0x2, 0xcf9); in ce4100_reset()
66 #define PCI_DEVICE_ID_INTEL_CE4100 0x0708
[all …]
/openbmc/linux/drivers/virt/acrn/
H A Dioreq.c43 int ret = 0; in ioreq_complete_request()
65 if (ret < 0) in ioreq_complete_request()
95 int ret = 0; in acrn_ioreq_request_default_complete()
113 * Return: 0 on success, <0 on error
122 "Invalid IO range [0x%llx,0x%llx]\n", start, end); in acrn_ioreq_range_add()
138 return 0; in acrn_ioreq_range_add()
194 if (ret < 0) { in ioreq_task()
203 return 0; in ioreq_task()
240 } while (has_pending && --retry > 0); in acrn_ioreq_request_clear()
241 if (retry == 0) in acrn_ioreq_request_clear()
[all …]
/openbmc/linux/arch/mips/pci/
H A Dops-sni.c19 * test for bus 0 and hope forwarding and decoding work properly for any
29 if (busno == 0 && devfn >= PCI_DEVFN(8, 0)) in set_config_address()
33 ((busno & 0xff) << 16) | in set_config_address()
34 ((devfn & 0xff) << 8) | in set_config_address()
35 (reg & 0xfc); in set_config_address()
60 return 0; in pcimt_read()
83 return 0; in pcimt_write()
96 outl((1 << 31) | ((busno & 0xff) << 16) | ((devfn & 0xff) << 8) | (reg & 0xfc), 0xcf8); in pcit_set_config_address()
106 * on bus 0 we need to check, whether there is a device answering in pcit_read()
110 if (bus->number == 0) { in pcit_read()
[all …]
/openbmc/qemu/tests/qtest/fuzz/
H A Di440fx_fuzz.c23 #define I440FX_PCI_HOST_BRIDGE_CFG 0xcf8
24 #define I440FX_PCI_HOST_BRIDGE_DATA 0xcfc
149 " -m 0 -display none";
/openbmc/qemu/include/hw/pci-host/
H A Dq35.h80 #define MCH_HOST_BRIDGE_CONFIG_ADDR 0xcf8
81 #define MCH_HOST_BRIDGE_CONFIG_DATA 0xcfc
84 #define MCH_HOST_BRIDGE_REVISION_DEFAULT 0x0
86 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES 0x50
88 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY 0xffff
89 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX 0xfff
92 #define MCH_HOST_BRIDGE_SMBASE_ADDR 0x30000
93 #define MCH_HOST_BRIDGE_F_SMBASE 0x9c
94 #define MCH_HOST_BRIDGE_F_SMBASE_QUERY 0xff
95 #define MCH_HOST_BRIDGE_F_SMBASE_IN_RAM 0x01
[all …]
/openbmc/linux/drivers/net/wireless/marvell/mwifiex/
H A Dpcie.h27 #define PCIE_VENDOR_ID_MARVELL (0x11ab)
28 #define PCIE_VENDOR_ID_V2_MARVELL (0x1b4b)
29 #define PCIE_DEVICE_ID_MARVELL_88W8766P (0x2b30)
30 #define PCIE_DEVICE_ID_MARVELL_88W8897 (0x2b38)
31 #define PCIE_DEVICE_ID_MARVELL_88W8997 (0x2b42)
33 #define PCIE8897_A0 0x1100
34 #define PCIE8897_B0 0x1200
35 #define PCIE8997_A0 0x10
36 #define PCIE8997_A1 0x11
37 #define CHIP_VER_PCIEUART 0x3
[all …]
/openbmc/linux/arch/mips/sni/
H A Dpcit.c32 PORT(0x3f8, 0),
33 PORT(0x2f8, 3),
46 PORT(0x3f8, 0),
47 PORT(0x2f8, 3),
48 PORT(0x3e8, 4),
49 PORT(0x2e8, 3),
63 .start = 0x70,
64 .end = 0x71,
86 .start = 0x00000000UL,
87 .end = 0x03bfffffUL,
[all …]

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