Home
last modified time | relevance | path

Searched +full:0 +full:xb8003000 (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnuvoton,wpcm450-pinctrl.yaml23 const: 0
31 "^gpio@[0-7]$":
36 Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18
41 minimum: 0
104 pattern: "^gpio1?[0-9]{1,2}$"
122 reg = <0xb8003000 0x1000>;
124 #size-cells = <0>;
126 gpio0: gpio@0 {
127 reg = <0>;
154 pinctrl-0 = <&pinctrl_uid>, <&pinmux_uid>;
/openbmc/qemu/hw/arm/
H A Dimx25_pdk.c38 * 0x00000000-0x7fffffff See i.MX25 SOC fr support
39 * 0x80000000-0x87ffffff RAM + Alias EMULATED
40 * 0x90000000-0x9fffffff RAM + Alias EMULATED
41 * 0xa0000000-0xa7ffffff Flash IGNORED
42 * 0xa8000000-0xafffffff Flash IGNORED
43 * 0xb0000000-0xb1ffffff SRAM IGNORED
44 * 0xb2000000-0xb3ffffff SRAM IGNORED
45 * 0xb4000000-0xb5ffffff CS4 IGNORED
46 * 0xb6000000-0xb8000fff Reserved IGNORED
47 * 0xb8001000-0xb8001fff SDRAM CTRL reg IGNORED
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx35/
H A Dimx-regs.h16 #define IRAM_BASE_ADDR 0x10000000 /* internal ram */
17 #define IRAM_SIZE 0x00020000 /* 128 KB */
19 #define LOW_LEVEL_SRAM_STACK 0x1001E000
24 #define AIPS1_BASE_ADDR 0x43F00000
26 #define MAX_BASE_ADDR 0x43F04000
27 #define EVTMON_BASE_ADDR 0x43F08000
28 #define CLKCTL_BASE_ADDR 0x43F0C000
29 #define I2C1_BASE_ADDR 0x43F80000
30 #define I2C3_BASE_ADDR 0x43F84000
31 #define ATA_BASE_ADDR 0x43F8C000
[all …]
/openbmc/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-wpcm450.dtsi24 #size-cells = <0>;
26 cpu@0 {
29 reg = <0>;
37 #clock-cells = <0>;
45 #clock-cells = <0>;
57 reg = <0xb0000000 0x200>;
62 reg = <0xb0000200 0x100>;
71 reg = <0xb8000000 0x20>;
76 pinctrl-0 = <&bsp_pins>;
82 reg = <0xb8000100 0x20>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx25/
H A Dimx-regs.h27 u32 cgr0; /* Clock Gating Control 0 */
33 u32 dcvr0; /* DPTC Comparator Value 0 */
37 u32 ltr0; /* Load Tracking 0 */
41 u32 ltbr0; /* Load Tracking Buffer 0 */
43 u32 pcmr0; /* Power Management Control 0 */
47 u32 lpimr0; /* Low Power Interrupt Mask 0 */
53 u32 ctl0; /* control 0 */
54 u32 cfg0; /* configuration 0 */
104 u32 res1[0x1f1];
106 u32 fuse_regs[0x20];
[all …]