Home
last modified time | relevance | path

Searched +full:0 +full:xaa000 (Results 1 – 15 of 15) sorted by relevance

/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dqoriq-fman3-0-1g-2.dtsi11 cell-index = <0xa>;
13 reg = <0x8a000 0x1000>;
17 cell-index = <0x2a>;
19 reg = <0xaa000 0x1000>;
25 reg = <0xe4000 0x1000>;
33 #size-cells = <0>;
35 reg = <0xe5000 0x1000>;
37 pcsphy2: ethernet-phy@0 {
38 reg = <0x0>;
/openbmc/qemu/tests/qemu-iotests/
H A D04625 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
60 local pattern=0
61 local cur_sec=0
63 for ((i=0;i<=$((sectors - 1));i++)); do
71 backing_io 0 32 write | $QEMU_IO "$TEST_IMG" | _filter_qemu_io
84 aio_write -P 10 0x18000 0x2000
87 aio_write -P 11 0x12000 0x2000
88 aio_write -P 12 0x1c000 0x2000
98 aio_write -P 20 0x28000 0x2000
[all …]
/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_vi_layer.h12 ((base) + 0x30 * (layer) + 0x0)
14 ((base) + 0x30 * (layer) + 0x4)
16 ((base) + 0x30 * (layer) + 0x8)
18 ((base) + 0x30 * (layer) + 0xc + 4 * (plane))
20 ((base) + 0x30 * (layer) + 0x18 + 4 * (plane))
22 ((base) + 0xe8)
24 ((base) + 0xf0)
26 ((base) + 0xf4)
28 ((base) + 0xf8)
30 ((base) + 0xfc)
[all …]
H A Dsun8i_mixer.h18 #define SUN8I_MIXER_GLOBAL_CTL 0x0
19 #define SUN8I_MIXER_GLOBAL_STATUS 0x4
20 #define SUN8I_MIXER_GLOBAL_DBUFF 0x8
21 #define SUN8I_MIXER_GLOBAL_SIZE 0xc
23 #define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0)
25 #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
27 #define DE2_MIXER_UNIT_SIZE 0x6000
28 #define DE3_MIXER_UNIT_SIZE 0x3000
30 #define DE2_BLD_BASE 0x1000
31 #define DE2_CH_BASE 0x2000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsnps,dwcmshc-sdhci.yaml77 reg = <0xfe310000 0x10000>;
78 interrupts = <0 25 0x4>;
83 #size-cells = <0>;
88 reg = <0xaa000 0x1000>;
89 interrupts = <0 25 0x4>;
94 #size-cells = <0>;
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-fman-1-1g-2.dtsi2 * QorIQ FMan 1g port #2 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0xa>;
39 reg = <0x8a000 0x1000>;
43 cell-index = <0x2a>;
45 reg = <0xaa000 0x1000>;
51 reg = <0xe4000 0x1000>;
59 #size-cells = <0>;
61 reg = <0xe5120 0xee0>;
64 reg = <0x8>;
H A Dqoriq-fman-0-1g-2.dtsi2 * QorIQ FMan 1g port #2 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0xa>;
39 reg = <0x8a000 0x1000>;
43 cell-index = <0x2a>;
45 reg = <0xaa000 0x1000>;
51 reg = <0xe4000 0x1000>;
59 #size-cells = <0>;
61 reg = <0xe5120 0xee0>;
64 reg = <0x8>;
H A Dqoriq-fman3-0-1g-2.dtsi2 * QorIQ FMan v3 1g port #2 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0xa>;
39 reg = <0x8a000 0x1000>;
43 cell-index = <0x2a>;
45 reg = <0xaa000 0x1000>;
51 reg = <0xe4000 0x1000>;
67 #size-cells = <0>;
69 reg = <0xe5000 0x1000>;
72 pcsphy2: ethernet-phy@0 {
73 reg = <0x0>;
H A Dqoriq-fman3-1-1g-2.dtsi2 * QorIQ FMan v3 1g port #2 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0xa>;
39 reg = <0x8a000 0x1000>;
43 cell-index = <0x2a>;
45 reg = <0xaa000 0x1000>;
51 reg = <0xe4000 0x1000>;
67 #size-cells = <0>;
69 reg = <0xe5000 0x1000>;
72 pcsphy10: ethernet-phy@0 {
73 reg = <0x0>;
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddisplay2.h94 u8 res[0xc];
112 #define SUNXI_DE2_MUX0_BASE (SUNXI_DE2_BASE + 0x100000)
113 #define SUNXI_DE2_MUX1_BASE (SUNXI_DE2_BASE + 0x200000)
115 #define SUNXI_DE2_MUX_GLB_REGS 0x00000
116 #define SUNXI_DE2_MUX_BLD_REGS 0x01000
117 #define SUNXI_DE2_MUX_CHAN_REGS 0x02000
118 #define SUNXI_DE2_MUX_CHAN_SZ 0x1000
119 #define SUNXI_DE2_MUX_VSU_REGS 0x20000
120 #define SUNXI_DE2_MUX_GSU1_REGS 0x30000
121 #define SUNXI_DE2_MUX_GSU2_REGS 0x40000
[all …]
/openbmc/linux/drivers/net/wireless/rsi/
H A Drsi_hal.h45 #define FLASH_SIZE_ADDR 0x04000016
46 #define PING_BUFFER_ADDRESS 0x19000
47 #define PONG_BUFFER_ADDRESS 0x1a000
48 #define SWBL_REGIN 0x41050034
49 #define SWBL_REGOUT 0x4105003c
50 #define PING_WRITE 0x1
51 #define PONG_WRITE 0x2
56 #define REGIN_VALID 0xA
57 #define REGIN_INPUT 0xA0
58 #define REGOUT_VALID 0xAB
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dfsl-fman.txt28 FMan block. The offset is 0xc4 from the beginning of the
29 Frame Processing Manager memory map (0xc3000 from the
44 DEVDISR[1] 1 0
49 DCFG_DEVDISR2[6] 1 0
56 DCFG_CCSR_DEVDISR2[24] 1 0
148 muram@0 {
150 ranges = <0 0x000000 0x28000>;
215 cell-index = <0x28>;
217 reg = <0xa8000 0x1000>;
221 cell-index = <0x8>;
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam33xx-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
4 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x400>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
[all …]
H A Dam437x-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
4 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x400>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Dgcc-sc8280xp.c113 .offset = 0x0,
116 .enable_reg = 0x52028,
117 .enable_mask = BIT(0),
128 { 0x1, 2 },
133 .offset = 0x0,
150 .offset = 0x2000,
153 .enable_reg = 0x52028,
165 .offset = 0x76000,
168 .enable_reg = 0x52028,
180 .offset = 0x1a000,
[all …]