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/openbmc/linux/arch/powerpc/boot/dts/
H A Dmvme5100.dts26 #size-cells = <0>;
30 reg = <0x0>;
44 reg = <0x0 0x20000000>;
51 ranges = <0x0 0xfef80000 0x10000>;
52 reg = <0xfef80000 0x10000>;
57 reg = <0x8000 0x80>;
68 reg = <0x8200 0x80>;
78 #address-cells = <0>;
82 reg = <0xf3f80000 0x40000>;
92 reg = <0xfec00000 0x400000>;
[all …]
H A Dstxssa8555.dts30 #size-cells = <0>;
32 PowerPC,8555@0 {
34 reg = <0x0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot
48 reg = <0x00000000 0x10000000>;
56 ranges = <0x0 0xe0000000 0x100000>;
[all …]
/openbmc/linux/sound/soc/codecs/
H A Drt274.h14 #define RT274_AUDIO_FUNCTION_GROUP 0x01
15 #define RT274_DAC_OUT0 0x02
16 #define RT274_DAC_OUT1 0x03
17 #define RT274_ADC_IN2 0x08
18 #define RT274_ADC_IN1 0x09
19 #define RT274_DIG_CVT 0x0a
20 #define RT274_DMIC1 0x12
21 #define RT274_DMIC2 0x13
22 #define RT274_MIC 0x19
23 #define RT274_LINE1 0x1a
[all …]
H A Drt286.h14 #define RT286_AUDIO_FUNCTION_GROUP 0x01
15 #define RT286_DAC_OUT1 0x02
16 #define RT286_DAC_OUT2 0x03
17 #define RT286_ADC_IN1 0x09
18 #define RT286_ADC_IN2 0x08
19 #define RT286_MIXER_IN 0x0b
20 #define RT286_MIXER_OUT1 0x0c
21 #define RT286_MIXER_OUT2 0x0d
22 #define RT286_DMIC1 0x12
23 #define RT286_DMIC2 0x13
[all …]
H A Drt298.h14 #define RT298_AUDIO_FUNCTION_GROUP 0x01
15 #define RT298_DAC_OUT1 0x02
16 #define RT298_DAC_OUT2 0x03
17 #define RT298_DIG_CVT 0x06
18 #define RT298_ADC_IN1 0x09
19 #define RT298_ADC_IN2 0x08
20 #define RT298_MIXER_IN 0x0b
21 #define RT298_MIXER_OUT1 0x0c
22 #define RT298_MIXER_OUT2 0x0d
23 #define RT298_DMIC1 0x12
[all …]
/openbmc/qemu/hw/audio/
H A Dgusemu_mixer.c45 for (count = 0; count < numsamples * 2; count++) in gus_mixvoices()
46 *(bufferpos + count) = 0; /* clear */ in gus_mixvoices()
50 if (!(GUSregb(GUS4cReset) & 0x01)) /* reset flag active? */ in gus_mixvoices()
53 for (Voice = 0; Voice <= (GUSregb(NumVoices) & 31); Voice++) in gus_mixvoices()
55 if (GUSvoice(wVSRControl) & 0x200) in gus_mixvoices()
56 GUSvoice(wVSRControl) |= 0x100; /* voice stop request */ in gus_mixvoices()
57 if (GUSvoice(wVSRVolRampControl) & 0x200) in gus_mixvoices()
58 GUSvoice(wVSRVolRampControl) |= 0x100; /* Volume ramp stop request */ in gus_mixvoices()
59 …if (!(GUSvoice(wVSRControl) & GUSvoice(wVSRVolRampControl) & 0x100)) /* neither voice nor volume c… in gus_mixvoices()
69 int PanningPos = (GUSvoice(wVSRPanning) >> 8) & 0xf; in gus_mixvoices()
[all …]
/openbmc/linux/drivers/crypto/aspeed/
H A Daspeed-hace.h19 #define ASPEED_HACE_SRC 0x00 /* Crypto Data Source Base Address Register */
20 #define ASPEED_HACE_DEST 0x04 /* Crypto Data Destination Base Address Register */
21 #define ASPEED_HACE_CONTEXT 0x08 /* Crypto Context Buffer Base Address Register */
22 #define ASPEED_HACE_DATA_LEN 0x0C /* Crypto Data Length Register */
23 #define ASPEED_HACE_CMD 0x10 /* Crypto Engine Command Register */
26 #define ASPEED_HACE_TAG 0x18 /* HACE Tag Register */
28 #define ASPEED_HACE_GCM_ADD_LEN 0x14 /* Crypto AES-GCM Additional Data Length Register */
29 #define ASPEED_HACE_GCM_TAG_BASE_ADDR 0x18 /* Crypto AES-GCM Tag Write Buff Base Address Reg */
31 #define ASPEED_HACE_STS 0x1C /* HACE Status Register */
33 #define ASPEED_HACE_HASH_SRC 0x20 /* Hash Data Source Base Address Register */
[all …]
/openbmc/linux/drivers/net/usb/
H A Dr8153_ecm.c10 #define OCP_BASE 0xe86c
26 if (ret < 0) in pla_read_word()
31 ret &= 0xffff; in pla_read_word()
39 u32 mask = 0xffff; in pla_write_word()
58 if (ret < 0) in pla_write_word()
76 ret = pla_write_word(dev, OCP_BASE, 0xa000); in r8153_ecm_mdio_read()
77 if (ret < 0) in r8153_ecm_mdio_read()
80 ret = pla_read_word(dev, 0xb400 + reg * 2); in r8153_ecm_mdio_read()
91 ret = pla_write_word(dev, OCP_BASE, 0xa000); in r8153_ecm_mdio_write()
92 if (ret < 0) in r8153_ecm_mdio_write()
[all …]
/openbmc/linux/arch/mips/sgi-ip22/
H A Dip22-nvram.c13 #define EEPROM_READ 0xc000 /* serial memory read */
14 #define EEPROM_WEN 0x9800 /* write enable before prog modes */
15 #define EEPROM_WRITE 0xa000 /* serial memory write */
16 #define EEPROM_WRALL 0x8800 /* write all registers */
17 #define EEPROM_WDS 0x8000 /* disable all programming */
18 #define EEPROM_PRREAD 0xc000 /* read protect register */
19 #define EEPROM_PREN 0x9800 /* enable protect register mode */
20 #define EEPROM_PRCLEAR 0xffff /* clear protect register */
21 #define EEPROM_PRWRITE 0xa000 /* write protect register */
22 #define EEPROM_PRDS 0x8000 /* disable protect register, forever */
[all …]
/openbmc/linux/drivers/staging/media/atomisp/pci/
H A Dif_defs.h19 #define HIVE_IF_FRAME_REQUEST 0xA000
20 #define HIVE_IF_LINES_REQUEST 0xB000
21 #define HIVE_IF_VECTORS_REQUEST 0xC000
/openbmc/qemu/tests/qemu-iotests/
H A D07725 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
57 aio_write -P 10 0x200 0x200
62 off=0x1000
66 aio_write -P 10 $((off + 0x200)) 0x200
68 aio_write -P 11 $((off + 0x400)) 0x200
73 off=$((off + 0x1000))
79 aio_write -P 10 0x5000 0x200
81 aio_write -P 11 0x5200 0x200
82 aio_write -P 12 0x5400 0x200
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc4357.dtsi18 cpu@0 {
26 reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
31 reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
/openbmc/linux/Documentation/devicetree/bindings/mailbox/
H A Dxgene-slimpro-mailbox.txt14 - interrupts: 8 interrupts must be from 0 to 7, interrupt 0 define the
15 the interrupt for mailbox channel 0 and interrupt 1 for
25 reg = <0x0 0x10540000 0x0 0xa000>;
27 interrupts = <0x0 0x0 0x4>,
28 <0x0 0x1 0x4>,
29 <0x0 0x2 0x4>,
30 <0x0 0x3 0x4>,
31 <0x0 0x4 0x4>,
32 <0x0 0x5 0x4>,
33 <0x0 0x6 0x4>,
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dpm8841.dtsi10 polling-delay = <0>;
40 reg = <0x4 SPMI_USID>;
42 #size-cells = <0>;
46 reg = <0xa000>;
49 gpio-ranges = <&pm8841_mpps 0 0 4>;
56 reg = <0x2400>;
57 interrupts = <4 0x24 0 IRQ_TYPE_EDGE_RISING>;
58 #thermal-sensor-cells = <0>;
64 reg = <0x5 SPMI_USID>;
66 #size-cells = <0>;
H A Dpma8084.dtsi8 pma8084_0: pma8084@0 {
10 reg = <0x0 SPMI_USID>;
12 #size-cells = <0>;
16 reg = <0x6000>,
17 <0x6100>;
19 interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
24 reg = <0x800>;
25 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
32 reg = <0xc000>;
34 gpio-ranges = <&pma8084_gpios 0 0 22>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dpmi8994.dtsi9 reg = <0x2 SPMI_USID>;
11 #size-cells = <0>;
15 reg = <0xc000>;
17 gpio-ranges = <&pmi8994_gpios 0 0 10>;
25 reg = <0xa000>;
27 gpio-ranges = <&pmi8994_mpps 0 0 4>;
36 reg = <0x3 SPMI_USID>;
38 #size-cells = <0>;
44 #size-cells = <0>;
56 reg = <0xd800>, <0xd900>;
[all …]
H A Dpmi8950.dtsi11 reg = <0x2 SPMI_USID>;
13 #size-cells = <0>;
17 reg = <0x3100>;
18 interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
20 #size-cells = <0>;
23 channel@0 {
62 reg = <0xa000>;
64 gpio-ranges = <&pmi8950_mpps 0 0 4>;
72 reg = <0xc000>;
74 gpio-ranges = <&pmi8950_gpios 0 0 2>;
[all …]
/openbmc/linux/Documentation/i2c/
H A Dten-bit-addresses.rst7 do not intersect: the 7 bit address 0x10 is not the same as the 10 bit
8 address 0x10 (though a single device could respond to both of them).
10 address space, namely 0xa000-0xa3ff. The leading 0xa (= 10) represents the
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sm8450-gpucc.yaml66 reg = <0 0x03d90000 0 0xa000>;
/openbmc/linux/drivers/pinctrl/qcom/
H A Dpinctrl-lpass-lpi.h18 #define LPI_SLEW_RATE_CTL_REG 0xa000
19 #define LPI_TLMM_REG_OFFSET 0x1000
20 #define LPI_SLEW_RATE_MAX 0x03
21 #define LPI_SLEW_BITS_SIZE 0x02
22 #define LPI_SLEW_RATE_MASK GENMASK(1, 0)
23 #define LPI_GPIO_CFG_REG 0x00
24 #define LPI_GPIO_PULL_MASK GENMASK(1, 0)
28 #define LPI_GPIO_VALUE_REG 0x04
29 #define LPI_GPIO_VALUE_IN_MASK BIT(0)
32 #define LPI_GPIO_BIAS_DISABLE 0x0
[all …]
/openbmc/qemu/linux-user/include/host/riscv/
H A Dhost-signal.h40 uint16_t insn = pinsn[0]; in host_signal_write()
43 switch (insn & 0xe003) { in host_signal_write()
44 case 0xa000: /* c.fsd */ in host_signal_write()
45 case 0xc000: /* c.sw */ in host_signal_write()
46 case 0xe000: /* c.sd (rv64) / c.fsw (rv32) */ in host_signal_write()
47 case 0xa002: /* c.fsdsp */ in host_signal_write()
48 case 0xc002: /* c.swsp */ in host_signal_write()
49 case 0xe002: /* c.sdsp (rv64) / c.fswsp (rv32) */ in host_signal_write()
54 switch (insn & 0x7f) { in host_signal_write()
55 case 0x23: /* store */ in host_signal_write()
[all …]
/openbmc/linux/drivers/usb/storage/
H A Dunusual_datafab.h9 UNUSUAL_DEV( 0x07c4, 0xa000, 0x0000, 0x0015,
13 0),
17 * using the current driver...the 0xffff is arbitrary since I
20 * The 0xa003 and 0xa004 devices in particular I'm curious about.
26 UNUSUAL_DEV( 0x07c4, 0xa001, 0x0000, 0xffff,
30 0),
33 UNUSUAL_DEV( 0x07c4, 0xa002, 0x0000, 0xffff,
39 UNUSUAL_DEV( 0x07c4, 0xa003, 0x0000, 0xffff,
43 0),
45 UNUSUAL_DEV( 0x07c4, 0xa004, 0x0000, 0xffff,
[all …]
/openbmc/linux/drivers/net/ethernet/apm/xgene-v2/
H A Dmac.h14 #define MAC_CONFIG_1 0xa000
15 #define MAC_CONFIG_2 0xa004
16 #define MII_MGMT_CONFIG 0xa020
17 #define MII_MGMT_COMMAND 0xa024
18 #define MII_MGMT_ADDRESS 0xa028
19 #define MII_MGMT_CONTROL 0xa02c
20 #define MII_MGMT_STATUS 0xa030
21 #define MII_MGMT_INDICATORS 0xa034
22 #define INTERFACE_CONTROL 0xa038
23 #define STATION_ADDR0 0xa040
[all …]
/openbmc/linux/arch/arm64/include/asm/
H A Ddebug-monitors.h16 #define DBG_MDSCR_SS (1 << 0)
24 #define DBG_ESR_EVT(x) (((x) >> 27) & 0x7)
27 #define DBG_ESR_EVT_HWBP 0x0
28 #define DBG_ESR_EVT_HWSS 0x1
29 #define DBG_ESR_EVT_HWWP 0x2
30 #define DBG_ESR_EVT_BRK 0x6
49 #define DBG_ESR_EVT_BKPT 0x4
50 #define DBG_ESR_EVT_VECC 0x5
52 #define AARCH32_BREAK_ARM 0x07f001f0
53 #define AARCH32_BREAK_THUMB 0xde01
[all …]
/openbmc/qemu/include/hw/display/
H A Dxlnx_dp.h43 #define DP_CORE_REG_OFFSET (0x0000)
44 #define DP_CORE_REG_ARRAY_SIZE (0x3B0 >> 2)
45 #define DP_AVBUF_REG_OFFSET (0xB000)
46 #define DP_AVBUF_REG_ARRAY_SIZE (0x238 >> 2)
47 #define DP_VBLEND_REG_OFFSET (0xA000)
48 #define DP_VBLEND_REG_ARRAY_SIZE (0x1E0 >> 2)
49 #define DP_AUDIO_REG_OFFSET (0xC000)
50 #define DP_AUDIO_REG_ARRAY_SIZE (0x50 >> 2)
51 #define DP_CONTAINER_SIZE (0xC050)

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