Searched +full:0 +full:xf8001000 (Results 1 – 5 of 5) sorted by relevance
22 reg = <0xf8001000 0x1000>;23 interrupts = <0 47 4>;
47 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;49 reg = <0xF8001000 0x1000>;
16 #size-cells = <0>;18 cpu0: cpu@0 {21 reg = <0>;50 interrupts = <0 5 4>, <0 6 4>;52 reg = <0xf8891000 0x1000>,53 <0xf8893000 0x1000>;75 reg = <0xf8007100 0x20>;76 interrupts = <0 7 4>;86 reg = <0xe0008000 0x1000>;87 interrupts = <0 28 4>;[all …]
13 #size-cells = <0>;15 cpu0: cpu@0 {18 reg = <0>;47 interrupts = <0 5 4>, <0 6 4>;49 reg = <0xf8891000 0x1000>,50 <0xf8893000 0x1000>;69 #size-cells = <0>;72 port@0 {73 reg = <0>;104 reg = <0xf8007100 0x20>;[all …]
59 #define MPCORE_PERIPHBASE 0xF8F0000060 #define ZYNQ_BOARD_MIDR 0x413FC09066 #define BOARD_SETUP_ADDR 0x10068 #define SLCR_LOCK_OFFSET 0x00469 #define SLCR_UNLOCK_OFFSET 0x00870 #define SLCR_ARM_PLL_OFFSET 0x10072 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d73 #define SLCR_XILINX_LOCK_KEY 0x767b75 #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */77 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \[all …]