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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dst,ssc-spi.yaml51 reg = <0x9840000 0x110>;
55 pinctrl-0 = <&pinctrl_spi0_default>;
58 #size-cells = <0>;
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstih407-family.dtsi22 reg = <0x45000000 0x00400000>;
28 reg = <0x44000000 0x01000000>;
35 #size-cells = <0>;
36 cpu@0 {
39 reg = <0>;
41 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
42 cpu-release-addr = <0x94100A4>;
45 operating-points = <1500000 0
46 1200000 0
47 800000 0
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dstih407-family.dtsi25 reg = <0x44000000 0x01000000>;
32 #size-cells = <0>;
33 cpu@0 {
36 reg = <0>;
38 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
39 cpu-release-addr = <0x94100A4>;
42 operating-points = <1500000 0
43 1200000 0
44 800000 0
45 500000 0>;
[all …]
H A Dhi3798cv200.dtsi29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x0 0x0>;
41 reg = <0x0 0x1>;
48 reg = <0x0 0x2>;
55 reg = <0x0 0x3>;
62 reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
63 <0x0 0xf1002000 0x0 0x100>; /* GICC */
64 #address-cells = <0>;
85 ranges = <0x0 0x0 0xf0000000 0x10000000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3798cv200.dtsi27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0x0 0x0>;
39 reg = <0x0 0x1>;
46 reg = <0x0 0x2>;
53 reg = <0x0 0x3>;
60 reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
61 <0x0 0xf1002000 0x0 0x2000>; /* GICC */
62 #address-cells = <0>;
83 ranges = <0x0 0x0 0xf0000000 0x10000000>;
[all …]