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/openbmc/linux/Documentation/devicetree/bindings/nvmem/
H A Dqcom,qfprom.yaml88 reg = <0 0x00784000 0 0x8ff>,
89 <0 0x00780000 0 0x7a0>,
90 <0 0x00782000 0 0x100>,
91 <0 0x00786000 0 0x1fff>;
100 reg = <0x25b 0x1>;
113 reg = <0 0x00784000 0 0x8ff>;
118 reg = <0x1eb 0x1>;
/openbmc/qemu/tests/tcg/i386/
H A Dtest-flags.c23 addr = mmap (NULL, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANON, -1, 0); in main()
24 *addr = 0x1234; in main()
36 assert((flags & 0xff) == 0xd7 && (flags_after & 0x8ff) == 0x17); in main()
/openbmc/linux/drivers/mfd/
H A Dtimberdale.h23 #define TIMB_REV_MAJOR 0x00
24 #define TIMB_REV_MINOR 0x04
25 #define TIMB_HW_CONFIG 0x08
26 #define TIMB_SW_RST 0x40
29 #define TIMB_HW_CONFIG_SPI_8BIT 0x80
31 #define TIMB_HW_VER_MASK 0x0f
32 #define TIMB_HW_VER0 0x00
33 #define TIMB_HW_VER1 0x01
34 #define TIMB_HW_VER2 0x02
35 #define TIMB_HW_VER3 0x03
[all …]
/openbmc/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2-kryo-cpu.yaml41 '^opp-?[0-9]+$':
54 0: MSM8996, speedbin 0
61 0-3: unused
62 4: MSM8996SG, speedbin 0
66 enum: [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
67 0x9, 0xd, 0xe, 0xf,
68 0x10, 0x20, 0x30, 0x70]
85 '^opp-?[0-9]+$':
101 #size-cells = <0>;
103 CPU0: cpu@0 {
[all …]
/openbmc/linux/drivers/ssb/
H A Ddriver_gige.c116 if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0)) in ssb_gige_pci_read_config()
146 if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0)) in ssb_gige_pci_write_config()
185 dev->pci_controller.io_map_base = 0x800; in ssb_gige_probe()
190 dev->io_resource.start = 0x800; in ssb_gige_probe()
191 dev->io_resource.end = 0x8FF; in ssb_gige_probe()
195 ssb_device_enable(sdev, 0); in ssb_gige_probe()
200 gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0); in ssb_gige_probe()
204 dev->mem_resource.end = base + 0x10000 - 1; in ssb_gige_probe()
218 gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068); in ssb_gige_probe()
231 dev->has_rgmii = 0; in ssb_gige_probe()
[all …]
/openbmc/linux/drivers/ata/
H A Dahci_imx.c28 IMX_TIMER1MS = 0x00e0,
30 IMX_P0PHYCR = 0x0178,
37 IMX_P0PHYSR = 0x017c,
39 IMX_P0PHYSR_CR_DATA_OUT = 0xffff << 0,
41 IMX_LANE0_OUT_STAT = 0x2003,
44 IMX_CLOCK_RESET = 0x7f3f,
45 IMX_CLOCK_RESET_RESET = 1 << 0,
47 IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET = 0x03,
48 IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET = 0x09,
49 IMX8QM_SATA_PHY_IMPED_RATIO_85OHM = 0x6c,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_AGE_CNTL 0x9bf
29 #define mmMC_ARB_RET_CREDITS2 0x9c0
30 #define mmMC_ARB_FED_CNTL 0x9c1
31 #define mmMC_ARB_GECC2_STATUS 0x9c2
32 #define mmMC_ARB_GECC2_MISC 0x9c3
33 #define mmMC_ARB_GECC2_DEBUG 0x9c4
34 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
35 #define mmMC_ARB_GECC2 0x9c9
36 #define mmMC_ARB_GECC2_CLI 0x9ca
[all …]
H A Dgmc_8_2_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_ATOMIC 0x9be
29 #define mmMC_ARB_AGE_CNTL 0x9bf
30 #define mmMC_ARB_RET_CREDITS2 0x9c0
31 #define mmMC_ARB_FED_CNTL 0x9c1
32 #define mmMC_ARB_GECC2_STATUS 0x9c2
33 #define mmMC_ARB_GECC2_MISC 0x9c3
34 #define mmMC_ARB_GECC2_DEBUG 0x9c4
35 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
36 #define mmMC_ARB_PERF_CID 0x9c6
[all …]
H A Dgmc_7_1_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_AGE_CNTL 0x9bf
29 #define mmMC_ARB_RET_CREDITS2 0x9c0
30 #define mmMC_ARB_FED_CNTL 0x9c1
31 #define mmMC_ARB_GECC2_STATUS 0x9c2
32 #define mmMC_ARB_GECC2_MISC 0x9c3
33 #define mmMC_ARB_GECC2_DEBUG 0x9c4
34 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
35 #define mmMC_ARB_PERF_CID 0x9c6
36 #define mmMC_ARB_GECC2 0x9c9
[all …]
H A Dgmc_8_1_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_ATOMIC 0x9be
29 #define mmMC_ARB_AGE_CNTL 0x9bf
30 #define mmMC_ARB_RET_CREDITS2 0x9c0
31 #define mmMC_ARB_FED_CNTL 0x9c1
32 #define mmMC_ARB_GECC2_STATUS 0x9c2
33 #define mmMC_ARB_GECC2_MISC 0x9c3
34 #define mmMC_ARB_GECC2_DEBUG 0x9c4
35 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
36 #define mmMC_ARB_PERF_CID 0x9c6
[all …]
/openbmc/linux/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h10 #define RF_DATA 0x1d4
12 #define rPMAC_Reset 0x100
13 #define rPMAC_TxStart 0x104
14 #define rPMAC_TxLegacySIG 0x108
15 #define rPMAC_TxHTSIG1 0x10c
16 #define rPMAC_TxHTSIG2 0x110
17 #define rPMAC_PHYDebug 0x114
18 #define rPMAC_TxPacketNum 0x118
19 #define rPMAC_TxIdle 0x11c
20 #define rPMAC_TxMACHeader0 0x120
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_8_0_enum.h28 DBG_BLOCK_ID_RESERVED = 0x0,
29 DBG_BLOCK_ID_DBG = 0x1,
30 DBG_BLOCK_ID_VMC = 0x2,
31 DBG_BLOCK_ID_PDMA = 0x3,
32 DBG_BLOCK_ID_CG = 0x4,
33 DBG_BLOCK_ID_SRBM = 0x5,
34 DBG_BLOCK_ID_GRBM = 0x6,
35 DBG_BLOCK_ID_RLC = 0x7,
36 DBG_BLOCK_ID_CSC = 0x8,
37 DBG_BLOCK_ID_SEM = 0x9,
[all …]
H A Dsmu_7_1_2_enum.h27 #define CG_SRBM_START_ADDR 0x600
28 #define CG_SRBM_END_ADDR 0x8ff
29 #define RCU_CCF_DWORDS0 0xa0
30 #define RCU_CCF_BITS0 0x1400
31 #define RCU_CCF_DWORDS1 0x0
32 #define RCU_CCF_BITS1 0x0
33 #define RCU_SAM_BYTES 0x2c
34 #define RCU_SAM_RTL_BYTES 0x2c
35 #define RCU_SMU_BYTES 0x14
36 #define RCU_SMU_RTL_BYTES 0x14
[all …]
H A Dsmu_7_1_1_enum.h27 #define CG_SRBM_START_ADDR 0x600
28 #define CG_SRBM_END_ADDR 0x8ff
29 #define RCU_CCF_DWORDS0 0x80
30 #define RCU_CCF_BITS0 0x1000
31 #define RCU_CCF_DWORDS1 0x0
32 #define RCU_CCF_BITS1 0x0
33 #define RCU_SAM_BYTES 0x0
34 #define RCU_SAM_RTL_BYTES 0x0
35 #define RCU_SMU_BYTES 0x0
36 #define RCU_SMU_RTL_BYTES 0x0
[all …]
H A Dsmu_7_1_0_enum.h27 #define CG_SRBM_START_ADDR 0x600
28 #define CG_SRBM_END_ADDR 0x8ff
29 #define RCU_CCF_DWORDS0 0x28
30 #define RCU_CCF_BITS0 0x500
31 #define RCU_CCF_DWORDS1 0x7f
32 #define RCU_CCF_BITS1 0x1000
33 #define RCU_SAM_BYTES 0x40
34 #define RCU_SAM_RTL_BYTES 0x40
35 #define KEYS_CHAIN_ADR 0x0
36 #define SAMU_KEY_SADR 0xa0
[all …]
H A Dsmu_7_1_3_enum.h27 #define CG_SRBM_START_ADDR 0x600
28 #define CG_SRBM_END_ADDR 0x8ff
29 #define RCU_CCF_DWORDS0 0xa0
30 #define RCU_CCF_BITS0 0x1400
31 #define RCU_SAM_BYTES 0x2c
32 #define RCU_SAM_RTL_BYTES 0x2c
33 #define RCU_SMU_BYTES 0x14
34 #define RCU_SMU_RTL_BYTES 0x14
35 #define SFP_CHAIN_ADDR 0x1
36 #define SFP_SADR 0x0
[all …]
/openbmc/linux/drivers/staging/rtl8712/
H A Drtl871x_mp_phy_regdef.h36 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
38 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
39 * 3. RF register 0x00-2E
44 * 1. Page1(0x100)
46 #define rPMAC_Reset 0x100
47 #define rPMAC_TxStart 0x104
48 #define rPMAC_TxLegacySIG 0x108
49 #define rPMAC_TxHTSIG1 0x10c
50 #define rPMAC_TxHTSIG2 0x110
51 #define rPMAC_PHYDebug 0x114
[all …]
/openbmc/linux/drivers/staging/rtl8723bs/include/
H A DHal8192CPhyReg.h41 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
43 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
44 /* 3. RF register 0x00-2E */
52 /* 1. Page1(0x100) */
54 #define rPMAC_Reset 0x100
55 #define rPMAC_TxStart 0x104
56 #define rPMAC_TxLegacySIG 0x108
57 #define rPMAC_TxHTSIG1 0x10c
58 #define rPMAC_TxHTSIG2 0x110
59 #define rPMAC_PHYDebug 0x114
[all …]
/openbmc/linux/arch/powerpc/kvm/
H A Dbook3s_paired_singles.c24 #define dprintk(...) do { } while(0);
63 #define OP_63_FCMPU 0
91 #define OP_4X_PS_CMPU0 0
125 #define SCALAR_NONE 0
126 #define SCALAR_HIGH (1 << 0)
131 #define GQR_ST_TYPE_MASK 0x00000007
132 #define GQR_ST_TYPE_SHIFT 0
133 #define GQR_ST_SCALE_MASK 0x00003f00
135 #define GQR_LD_TYPE_MASK 0x00070000
137 #define GQR_LD_SCALE_MASK 0x3f000000
[all …]
/openbmc/linux/drivers/scsi/
H A Dnsp32.c45 static int trans_mode = 0; /* default: BIOS */
46 module_param (trans_mode, int, 0);
47 MODULE_PARM_DESC(trans_mode, "transfer mode (0: BIOS(default) 1: Async 2: Ultra20M");
51 static bool auto_param = 0; /* default: ON */
52 module_param (auto_param, bool, 0);
53 MODULE_PARM_DESC(auto_param, "AutoParameter mode (0: ON(default) 1: OFF)");
56 module_param (disc_priv, bool, 0);
57 MODULE_PARM_DESC(disc_priv, "disconnection privilege mode (0: ON 1: OFF(default))");
126 {0,0,},
140 {0x1, 0, 0x0c, 0x0c, SMPL_40M}, /* 20.0 : 50ns, 25ns */
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/westmereep-dp/
H A Dcache.json4 "EventCode": "0x63",
7 "UMask": "0x2"
11 "EventCode": "0x63",
14 "UMask": "0x1"
18 "EventCode": "0x51",
21 "UMask": "0x4"
25 "EventCode": "0x51",
28 "UMask": "0x2"
32 "EventCode": "0x51",
35 "UMask": "0x8"
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/westmereex/
H A Dcache.json4 "EventCode": "0x63",
7 "UMask": "0x2"
11 "EventCode": "0x63",
14 "UMask": "0x1"
18 "EventCode": "0x51",
21 "UMask": "0x4"
25 "EventCode": "0x51",
28 "UMask": "0x2"
32 "EventCode": "0x51",
35 "UMask": "0x8"
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/nehalemep/
H A Dcache.json4 "EventCode": "0x63",
7 "UMask": "0x2"
11 "EventCode": "0x63",
14 "UMask": "0x1"
18 "EventCode": "0x51",
21 "UMask": "0x4"
25 "EventCode": "0x51",
28 "UMask": "0x2"
32 "EventCode": "0x51",
35 "UMask": "0x8"
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/nehalemex/
H A Dcache.json4 "EventCode": "0x63",
7 "UMask": "0x2"
11 "EventCode": "0x63",
14 "UMask": "0x1"
18 "EventCode": "0x51",
21 "UMask": "0x4"
25 "EventCode": "0x51",
28 "UMask": "0x2"
32 "EventCode": "0x51",
35 "UMask": "0x8"
[all …]
/openbmc/u-boot/include/
H A Dec_commands.h37 #define EC_PROTO_VERSION 0x00000002
43 #define EC_LPC_ADDR_ACPI_DATA 0x62
44 #define EC_LPC_ADDR_ACPI_CMD 0x66
47 #define EC_LPC_ADDR_HOST_DATA 0x200
48 #define EC_LPC_ADDR_HOST_CMD 0x204
52 #define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */
53 #define EC_LPC_ADDR_HOST_PARAM 0x804 /* For version 2 params; size is
56 #define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */
57 #define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */
59 /* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
[all …]

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