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/openbmc/linux/Documentation/devicetree/bindings/arm/hisilicon/controller/
H A Dhi3798cv200-perictrl.yaml48 reg = <0x8a20000 0x1000>;
51 ranges = <0x0 0x8a20000 0x1000>;
55 reg = <0x850 0x8>;
58 resets = <&crg 0x188 4>;
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dphy-hi3798cv200-combphy.txt37 reg = <0x8a20000 0x1000>;
40 ranges = <0x0 0x8a20000 0x1000>;
44 reg = <0x850 0x8>;
47 resets = <&crg 0x188 4>;
53 reg = <0x858 0x8>;
56 resets = <&crg 0x188 12>;
57 hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
H A Dphy-hisi-inno-usb2.txt14 - #size-cells: Must be 0.
22 - #phy-cells: Defined by generic PHY bindings. Must be 0.
31 reg = <0x8a20000 0x1000>;
34 ranges = <0x0 0x8a20000 0x1000>;
38 reg = <0x120 0x4>;
40 resets = <&crg 0xbc 4>;
42 #size-cells = <0>;
44 usb2_phy1_port0: phy@0 {
45 reg = <0>;
46 #phy-cells = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3798cv200.dtsi27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0x0 0x0>;
39 reg = <0x0 0x1>;
46 reg = <0x0 0x2>;
53 reg = <0x0 0x3>;
60 reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
61 <0x0 0xf1002000 0x0 0x2000>; /* GICC */
62 #address-cells = <0>;
83 ranges = <0x0 0x0 0xf0000000 0x10000000>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dhi3798cv200.dtsi29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x0 0x0>;
41 reg = <0x0 0x1>;
48 reg = <0x0 0x2>;
55 reg = <0x0 0x3>;
62 reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
63 <0x0 0xf1002000 0x0 0x100>; /* GICC */
64 #address-cells = <0>;
85 ranges = <0x0 0x0 0xf0000000 0x10000000>;
[all …]