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Searched +full:0 +full:x80840000 (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/powerpc/include/asm/
H A De300.h9 #define PVR_E300C1 0x80830000
10 #define PVR_E300C2 0x80840000
11 #define PVR_E300C3 0x80850000
12 #define PVR_E300C4 0x80860000
15 * Hardware Implementation-Dependent Register 0 (HID0)
19 #define HID0_MASK_MACHINE_CHECK 0x00000000
20 #define HID0_ENABLE_MACHINE_CHECK 0x80000000
22 #define HID0_DISABLE_CACHE_PARITY 0x00000000
23 #define HID0_ENABLE_CACHE_PARITY 0x40000000
25 #define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_default.h26 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
27 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
28 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
29 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
32 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
33 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
34 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af0107
35 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044
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H A Dgc_10_3_0_default.h27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
36 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
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/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-ep9301.yaml70 reg = <0x80840000 0x04>,
71 <0x80840010 0x04>,
72 <0x80840090 0x1c>;
83 reg = <0x80840004 0x04>,
84 <0x80840014 0x04>,
85 <0x808400ac 0x1c>;
96 reg = <0x80840008 0x04>,
97 <0x80840018 0x04>;
105 reg = <0x8084000c 0x04>,
106 <0x8084001c 0x04>;
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/openbmc/u-boot/arch/arm/include/asm/arch-ep93xx/
H A Dep93xx.h24 #define EP93XX_AHB_BASE 0x80000000
25 #define EP93XX_APB_BASE 0x80800000
28 * 0x80000000 - 0x8000FFFF: DMA
30 #define DMA_OFFSET 0x000000
73 * 0x80010000 - 0x8001FFFF: Ethernet MAC
75 #define MAC_OFFSET 0x010000
155 #define SELFCTL_RESET (1 << 0)
186 #define BMCTL_RXEN (1 << 0)
191 #define BMSTS_QID_MASK 0x07
192 #define BMSTS_QID_RXDATA 0x00
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/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsc7180-acer-aspire1.dts34 reg = <0x0 0x80840000 0 0x2000>;
39 reg = <0x0 0x85b00000 0 0x500000>;
44 reg = <0x0 0x86000000 0x0 0x2000000>;
49 reg = <0x0 0x8e400000 0x0 0x2800000>;
54 reg = <0x0 0x93900000 0x0 0x200000>;
63 pinctrl-0 = <&amp_sd_mode_default>;
66 #sound-dai-cells = <0>;
74 pinctrl-0 = <&soc_bkoff_default>;
87 pinctrl-0 = <&reg_edp_1p2_en_default>;
102 pinctrl-0 = <&reg_edp_1p8_en_default>;
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