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/openbmc/qemu/tests/tcg/arm/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
H A Dfcvt.ref4 00 SINGLE: -nan / 0xffa00000 (0 => OK)
5 00 HALF: 0xff00 (0x1 => INVALID)
6 01 SINGLE: -nan / 0xffc00000 (0 => OK)
7 01 HALF: 0xfe00 (0 => OK)
8 02 SINGLE: -inf / 0xff800000 (0 => OK)
9 02 HALF: 0xfc00 (0 => OK)
10 03 SINGLE: -3.40282346638528859812e+38 / 0xff7fffff (0 => OK)
11 03 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
12 04 SINGLE: -1.11100004769645909791e+31 / 0xf30c3a59 (0 => OK)
13 04 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
[all …]
/openbmc/qemu/tests/tcg/loongarch64/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
/openbmc/qemu/tests/tcg/aarch64/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
H A Dfcvt.ref4 00 SINGLE: -nan / 0xffa00000 (0 => OK)
5 00 HALF: 0xff00 (0x1 => INVALID)
6 01 SINGLE: -nan / 0xffc00000 (0 => OK)
7 01 HALF: 0xfe00 (0 => OK)
8 02 SINGLE: -inf / 0xff800000 (0 => OK)
9 02 HALF: 0xfc00 (0 => OK)
10 03 SINGLE: -3.40282346638528859812e+38 / 0xff7fffff (0 => OK)
11 03 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
12 04 SINGLE: -1.11100004769645909791e+31 / 0xf30c3a59 (0 => OK)
13 04 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
[all …]
/openbmc/qemu/tests/tcg/hexagon/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffffffff) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffffffff) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffffffff) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffffffff) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffffffff) flags=OK (1/1)
[all …]
/openbmc/qemu/tests/tcg/ppc64le/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffc00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffc00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,k3-dsp-rproc.yaml148 mailbox0_cluster3: mailbox-0 {
160 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
161 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */
162 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
163 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */
168 reg = <0x4d 0x80800000 0x00 0x00048000>,
169 <0x4d 0x80e00000 0x00 0x00008000>,
170 <0x4d 0x80f00000 0x00 0x00008000>;
174 ti,sci-proc-ids = <0x03 0xFF>;
185 reg = <0x00 0x64800000 0x00 0x00080000>,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Drockchip-dw-pcie.yaml102 const: 0
174 reg = <0x3 0xc0800000 0x0 0x390000>,
175 <0x0 0xfe280000 0x0 0x10000>,
176 <0x3 0x80000000 0x0 0x100000>;
178 bus-range = <0x20 0x2f>;
194 msi-map = <0x2000 &its 0x2000 0x1000>;
199 ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
200 <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
208 #address-cells = <0>;
/openbmc/u-boot/configs/
H A Dvexpress_ca15_tc2_defconfig3 CONFIG_SYS_TEXT_BASE=0x80800000
30 CONFIG_SMC911X_BASE=0x1a000000
33 CONFIG_CONS_INDEX=0
H A Dvexpress_ca5x2_defconfig3 CONFIG_SYS_TEXT_BASE=0x80800000
29 CONFIG_SMC911X_BASE=0x1a000000
32 CONFIG_CONS_INDEX=0
/openbmc/u-boot/doc/imx/habv4/script_examples/
H A DgenIVT.pl4 print $out pack("V", 0x412000D1); # Signature
5 print $out pack("V", 0x80800000); # Load Address (*load_address)
6 print $out pack("V", 0x0); # Reserved
7 print $out pack("V", 0x0); # DCD pointer
8 print $out pack("V", 0x0); # Boot Data
9 print $out pack("V", 0x80EEA000); # Self Pointer (*ivt)
10 print $out pack("V", 0x80EEA020); # CSF Pointer (*csf)
11 print $out pack("V", 0x0); # Reserved
/openbmc/linux/arch/arm/mach-ep93xx/
H A Dep93xx-regs.h14 #define EP93XX_AHB_PHYS_BASE 0x80000000
15 #define EP93XX_AHB_VIRT_BASE 0xfef00000
16 #define EP93XX_AHB_SIZE 0x00100000
21 #define EP93XX_APB_PHYS_BASE 0x80800000
22 #define EP93XX_APB_VIRT_BASE 0xfed00000
23 #define EP93XX_APB_SIZE 0x00200000
29 #define EP93XX_UART1_PHYS_BASE EP93XX_APB_PHYS(0x000c0000)
30 #define EP93XX_UART1_BASE EP93XX_APB_IOMEM(0x000c0000)
32 #define EP93XX_UART2_PHYS_BASE EP93XX_APB_PHYS(0x000d0000)
33 #define EP93XX_UART2_BASE EP93XX_APB_IOMEM(0x000d0000)
[all …]
/openbmc/u-boot/doc/imx/habv4/csf_examples/additional_images/
H A Dcsf_additional_images.txt4 Engine Configuration = 0
12 Source index = 0
22 Verification index = 0
32 Blocks = 0x80800000 0x00000000 0x80EEA020 "zImage", \
33 0x83800000 0x00000000 0x8380B927 "imx7d-sdb.dtb", \
34 0x84000000 0x00000000 0x840425B8 "uTee-7dsdb"
/openbmc/u-boot/include/configs/
H A Dmx7_common.h25 #define CONFIG_SYS_BOOTM_LEN 0x1000000
30 #define CONFIG_LOADADDR 0x80800000
48 #define CONFIG_ARMV7_SECURE_BASE 0x00900000
54 #define CONFIG_CSF_SIZE 0x2000
H A Dqemu-mips.h21 "panic=1\0" \
22 "bootfile=/tftpboot/vmlinux\0" \
23 "load=tftp 80500000 ${u-boot}\0" \
38 #define CONFIG_DRIVER_NE2000_BASE 0xb4000300
43 #define CONFIG_SYS_NS16550_COM1 0xb40003f8
50 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
51 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
52 #define CONFIG_SYS_ATA_DATA_OFFSET 0
53 #define CONFIG_SYS_ATA_REG_OFFSET 0
54 #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
[all …]
H A Dti814x_evm.h32 "loadaddr=0x80200000\0" \
33 "fdtaddr=0x80F80000\0" \
34 "rdaddr=0x81000000\0" \
35 "bootfile=/boot/uImage\0" \
36 "fdtfile=\0" \
37 "console=ttyO0,115200n8\0" \
38 "optargs=\0" \
39 "mmcdev=0\0" \
40 "mmcroot=/dev/mmcblk0p2 ro\0" \
41 "mmcrootfstype=ext4 rootwait\0" \
[all …]
H A Dbur_am335x_common.h20 #define CONFIG_SYS_NS16550_COM1 0x44e09000
31 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
38 * area between 0x402F0400 and 0x4030B800 as a download area and
39 * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also
44 #define CONFIG_SPL_TEXT_BASE 0x402F0400
56 * Our DDR memory always starts at 0x80000000 and U-Boot shall have
59 #define CONFIG_SYS_LOAD_ADDR 0x80000000
63 * always, even when we have more. We always start at 0x80000000,
66 #define CONFIG_SYS_SDRAM_BASE 0x80000000
82 * 0x80800000 for legacy reasons (to not conflict with older SPLs). We
[all …]
H A Dwoodburn_common.h44 #define CONFIG_SYS_SPD_BUS_NUM 0
51 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
55 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
74 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
81 #define CONFIG_FEC_MXC_PHYADDR 0x1
91 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
92 #define CONFIG_SYS_MEMTEST_END 0x10000
159 "netdev=eth0\0" \
161 "nfsroot=${serverip}:${rootpath}\0" \
162 "ramargs=setenv bootargs root=/dev/ram rw\0" \
[all …]
H A Dmx35pdk.h50 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08
57 #define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69
75 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
88 #define CONFIG_FEC_MXC_PHYADDR 0x1F
96 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
97 #define CONFIG_SYS_MEMTEST_END 0x10000
110 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
165 #define CONFIG_MXC_USB_PORT 0
172 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
182 "netdev=eth1\0" \
[all …]
/openbmc/linux/arch/s390/kernel/
H A Duprobes.c42 return 0; in arch_uprobe_pre_xol()
58 return 0; in check_per_event()
60 if (control == 0) in check_per_event()
63 if ((control & 0x20200000) && (cause & 0x2000)) in check_per_event()
65 if (cause & 0x8000) { in check_per_event()
67 if ((control & 0x80800000) == 0x80000000) in check_per_event()
70 if (((control & 0x80800000) == 0x80800000) && in check_per_event()
75 return 0; in check_per_event()
91 int reg = (auprobe->insn[0] & 0xf0) >> 4; in arch_uprobe_post_xol()
96 int ilen = insn_length(auprobe->insn[0] >> 8); in arch_uprobe_post_xol()
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
/openbmc/u-boot/doc/
H A DREADME.ubispl60 #define SPL_FINFO_ADDR 0x80800000
61 #define SPL_DTB_LOAD_ADDR 0x81800000
62 #define SPL_KERNEL_LOAD_ADDR 0x82000000
68 .vol_id = 0, /* kernel volume */
91 * part_spl { .start = 0, .end = 4 }
/openbmc/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8192e.c36 {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7},
37 {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00},
38 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
39 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
40 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
41 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
42 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
43 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
44 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
45 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-ep93xx/
H A Dep93xx.h24 #define EP93XX_AHB_BASE 0x80000000
25 #define EP93XX_APB_BASE 0x80800000
28 * 0x80000000 - 0x8000FFFF: DMA
30 #define DMA_OFFSET 0x000000
73 * 0x80010000 - 0x8001FFFF: Ethernet MAC
75 #define MAC_OFFSET 0x010000
155 #define SELFCTL_RESET (1 << 0)
186 #define BMCTL_RXEN (1 << 0)
191 #define BMSTS_QID_MASK 0x07
192 #define BMSTS_QID_RXDATA 0x00
[all …]

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