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/openbmc/u-boot/arch/arm/include/asm/arch-mxs/
H A Dregs-base.h21 #define MXS_ICOLL_BASE 0x80000000
22 #define MXS_APBH_BASE 0x80004000
23 #define MXS_ECC8_BASE 0x80008000
24 #define MXS_BCH_BASE 0x8000A000
25 #define MXS_GPMI_BASE 0x8000C000
26 #define MXS_SSP0_BASE 0x80010000
27 #define MXS_SSP1_BASE 0x80034000
28 #define MXS_ETM_BASE 0x80014000
29 #define MXS_PINCTRL_BASE 0x80018000
30 #define MXS_DIGCTL_BASE 0x8001C000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/nvmem/
H A Dmxs-ocotp.yaml42 reg = <0x8002c000 0x2000>;
/openbmc/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx23.dtsi32 #size-cells = <0>;
34 cpu@0 {
37 reg = <0>;
45 reg = <0x80000000 0x80000>;
52 reg = <0x80000000 0x40000>;
59 reg = <0x80000000 0x2000>;
64 reg = <0x80004000 0x2000>;
65 interrupts = <0>, <14>, <20>, <0>,
73 reg = <0x80008000 0x2000>;
81 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
[all …]
H A Dimx28.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
56 reg = <0x80000000 0x80000>;
63 reg = <0x80000000 0x3c900>;
70 reg = <0x80000000 0x2000>;
74 reg = <0x80002000 0x2000>;
83 reg = <0x80004000 0x2000>;
87 <87>, <86>, <0>, <0>;
94 reg = <0x80006000 0x800>;
[all …]